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Eiji Yoshiya

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2020 – today

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2022
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Eiji Yoshiya, Tomoya Nakanishi, Tsuyoshi Isshiki:
Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(7): 1061-1069 (2022)
2021
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Eiji Yoshiya, Tomoya Nakanishi, Tsuyoshi Isshiki:
RTL Design Framework for Embedded Processor by using C++ Description. DATE 2021: 1208-1211

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