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ORCIDJae-Kyung Wee
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2010 – 2019
- 2013
[j10]Ji-Hoon Lim, Won-Young Jung, Yong-Ju Kim, Inchae Song, Jae-Kyung Wee:
A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique. IEICE Trans. Electron. 96-C(2): 277-284 (2013)- 2012
- [c6]Young San Shin, Seongsoo Lee, Jae-Kyung Wee:
Current readout circuit using two-stage amplification method for 64-channel CNT arrays. ISCAS 2012: 854-857 - [c5]Young-Kyun Park, Ji-Hoon Lim, Jae-Kyung Wee, Inchae Song:
One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique. ISOCC 2012: 513-516 - 2011
- [j9]Young San Shin, Jae-Kyung Wee, Jong-Chan Ha, Ji-Hoon Lim, Yong-Ju Kim, Young-Sang Son:
A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. J. Circuits Syst. Comput. 20(4): 741-756 (2011)
2000 – 2009
- 2008
- [j8]Won-Young Jung, Hyungon Kim, Yong-Ju Kim, Jae-Kyung Wee:
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1177-1184 (2008) - 2007
- [j7]Ji-Hoon Lim, Jong-Chan Ha, Won-Young Jung, Yong-Ju Kim, Jae-Kyung Wee:
A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips. IEICE Trans. Electron. 90-C(3): 644-648 (2007) - 2006
- [j6]Yong-Ju Kim, Won-Young Jung, Jae-Kyung Wee:
Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards. IEICE Trans. Electron. 89-C(7): 1097-1105 (2006) - 2005
- [j5]Seongsoo Lee, Min-Cheol Hong, Jae-Kyung Wee:
Low-Hardware-Cost Motion Estimation with Large Search Range for VLSI Multimedia Processors. IEICE Trans. Inf. Syst. 88-D(9): 2177-2182 (2005) - [c4]Gang-Hoon Seo, Won-Yong Jung, Seongsoo Lee, Jae-Kyung Wee:
Pipelined Bidirectional Bus Architecture for Embedded Multimedia SoCs. EUC 2005: 350-359 - [c3]Yong-Ju Jang, Yoan Shin, Min-Cheol Hong, Jae-Kyung Wee, Seongsoo Lee:
Low-Power 32bit×32bit Multiplier Design with Pipelined Block-Wise Shutdown. HiPC 2005: 398-406 - [c2]Gyu-Sung Yeon, Chi-Hun Jun, Tae-Jin Hwang, Seongsoo Lee, Jae-Kyung Wee:
Low-Power MPEG-4 Motion Estimator Design for Deep Sub-Micron Multimedia SoC. KES (3) 2005: 449-455 - 2004
- [c1]Gyu-Sung Yeon, Chi-Hun Jun, Tae-Jin Hwang, Seongsoo Lee, Jae-Kyung Wee:
Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC. Circuits, Signals, and Systems 2004: 85-89 - 2002
- [j4]Jae-Kyung Wee, Kyeong-Sik Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, Jong-Doo Joo, Jin-Yong Chung:
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. IEEE J. Solid State Circuits 37(2): 251-254 (2002) - [j3]Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo-Hwan Cho, Pil Soo Lee, Jin-Hong Ahn, Jin-Yong Chung:
A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM. IEEE J. Solid State Circuits 37(6): 726-734 (2002) - [j2]Sanghoon Hong, Sejun Kim, Jae-Kyung Wee, Seongsoo Lee:
Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier. IEEE J. Solid State Circuits 37(10): 1356-1360 (2002) - 2000
- [j1]Jae-Kyung Wee, Woodward Yang, Eui-Kyu Ryou, Joe-Sun Choi, Seung-Han Ahn, Jin-Yong Chung, Sea-Chung Kim:
An antifuse EPROM circuitry scheme for field-programmable repair in DRAM. IEEE J. Solid State Circuits 35(10): 1408-1414 (2000)
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