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2020 – today
- 2023
[j6]Bo Yi
, Yi Xu, LiTian Zheng, Junji Cheng, Haimeng Huang, MouFu Kong, Hongqiang Yang:
Modeling and simulation of an insulated-gate HEMT using p-SnO2 gate for high VTH design. Microelectron. J. 139: 105895 (2023)- [c6]Bo Yi, Haimeng Huang, Haoran Hu, MouFu Kong, Yilin Guo, Wenkun Shi, Junji Cheng, Hongqiang Yang:
Comprehensive Comparison of Temperature Performances for SiC Trench MOSFET with Integrated Side-wall Schottky Diode and Heterojunction. ASICON 2023: 1-4 - [c5]Zonghao Zhang, Xi Wang, Keqiang Ma, Siliang Wang, Chenxing Wang, Haoyang Zhou, Haimeng Huang, Junji Cheng, Bo Yi, Hongqiang Yang:
Temperature Dependent Optimization for Specific On-Resistance for 900 V Superjunction MOSFETs: Numerical Calculation and Comparison. ASICON 2023: 1-4 - 2021
- [c4]Zheng Wu, Chao Xia, Bo Yi, Junji Cheng, Haimeng Huang, Moufu Kong, Hongqiang Yang, Wenkun Shi:
A split-gate SiC trench MOSFET with embedded unipolar diode for improved performances. ASICON 2021: 1-4 - [c3]Bo Yi, Zheng Wu, Junji Cheng, Haimeng Huang, Moufu Kong, Hongqiang Yang:
A Vertical Thin Layer pLDMOS with Linear doping realizing ultralow Ron, sp. ASICON 2021: 1-4 - 2020
- [j5]Junji Cheng, Jingjie Lin, Weizhen Chen, Shiying Wu, Haimeng Huang, Bo Yi:
Lateral Power Fin MOSFET With a High-k Passivation for Ultra-Low On-Resistance. IEEE Access 8: 48991-48999 (2020) - [j4]Bo Yi, Yi Feng Peng, Qing Zhao, MouFu Kong, Junji Cheng, Haimeng Huang:
Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer. IEICE Electron. Express 17(2): 20190673 (2020)
2010 – 2019
- 2019
- [j3]Haimeng Huang, Jun Huang, Huan Hu, Junji Cheng, Bo Yi:
Analytical Models of Breakdown Voltage and Specific On-Resistance for Vertical GaN Unipolar Devices. IEEE Access 7: 140383-140390 (2019) - [j2]Bo Yi, Hao Hu, Jia Lin, Junji Cheng, Haimeng Huang, MouFu Kong:
SiC trench MOSFET with integrated side-wall Schottky barrier diode having P+ electric field shield. IEICE Electron. Express 16(5): 20181135 (2019) - [j1]Jingjie Lin, Ping Li, Junji Cheng, Jiayu Wu, Bo Yi, Xingbi Chen:
A novel snapback-free reverse-conducting (RC) SOI-LIGBT with a built-in thyristor. IEICE Electron. Express 16(24): 20190626 (2019) - 2018
- [c2]Junji Cheng, Ping Li, Weizhen Chen, Bo Yi, Xingbi Chen:
Simulation study of a deep-trench LDMOS with bilateral super-junction drift regions. MIPRO 2018: 54-59 - [c1]Weizhen Chen, Junji Cheng, Jingjie Lin, Xingbi Chen:
Simulation study on the high-k SJ-VDMOS with gradient side-wall. MIPRO 2018: 60-65
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