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2020 – today
- 2024
[j8]Guangchao Zhao
, Zhiwei Zeng, Xingli Wang, Abdelrahman G. Qoutb, Philippe Coquet, Eby G. Friedman, Beng Kang Tay, Mingqiang Huang:
Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms. IEEE Trans. Emerg. Top. Comput. 12(3): 826-839 (2024)- [c11]Kai Li, Hantao Huang, Mingqiang Huang, Chenchen Ding, Longyang Lin, Liebing Ni, Hao Yu:
A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS. CICC 2024: 1-2 - [c10]Shuxin Yang, Chenchen Ding, Mingqiang Huang, Kai Li, Chenghao Li, Zikun Wei, Sixiao Huang, Jingyao Dong, Liuyang Zhang, Hao Yu:
LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA. FCCM 2024: 90-96 - [i3]Mingqiang Huang, Ao Shen, Kai Li, Haoxiang Peng, Boyu Li, Hao Yu:
EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. CoRR abs/2407.21325 (2024) - 2023
- [j7]Quan Cheng, Mingqiang Huang, Changhai Man, Ao Shen, Liuyao Dai, Hao Yu, Masanori Hashimoto:
Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3978-3991 (2023) - [j6]Mingqiang Huang, Junyi Luo, Chenchen Ding, Zikun Wei, Sixiao Huang, Hao Yu:
An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5289-5301 (2023) - [j5]Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao, Masanori Hashimoto, Hao Yu:
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2246-2250 (2023) - [c9]Jiahao Chen, Wanbo Hu, Wenling Ma, Zhilin Zhang, Mingqiang Huang:
Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet. AICAS 2023: 1-5 - [c8]Wenling Ma, Lianzheng Li, Ziye Li, Guangchao Zhao, Xiaojing Long, Mingqiang Huang:
RRAM-Based Precision-Scaleable Computing-In-Memory Scheme and Its Error Correction Approach. AICAS 2023: 1-5 - [c7]Mingqiang Huang, Yucen Liu, Sixiao Huang, Kai Li, Qiuping Wu, Hao Yu:
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. FPGA 2023: 229 - 2022
- [j4]Dingbang Liu, Haoxiang Zhou, Wei Mao, Jun Liu, Yuliang Han, Changhai Man, Qiuping Wu, Zhiru Guo, Mingqiang Huang, Shaobo Luo, Mingsong Lv, Quan Chen, Hao Yu:
An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 821-834 (2022) - [j3]Mingqiang Huang, Yucen Liu, Changhai Man, Kai Li, Quan Cheng, Wei Mao, Hao Yu:
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9): 3619-3631 (2022) - [j2]Wei Mao, Liuyao Dai, Kai Li, Quan Cheng, Yuhang Wang, Laimin Du, Shaobo Luo, Mingqiang Huang, Hao Yu:
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 30(12): 1878-1890 (2022) - [c6]Lunshuai Pan, Peng Xue, Hongxing Li, Litao Sun, Mingqiang Huang:
A General-Purpose and Configurable Planar Data Processor for Energy-Efficient Pooling Computation. AICAS 2022: 33-36 - [c5]Kai Li, Junzhuo Zhou, Yuhang Wang, Junyi Luo, Zhengke Yang, Shuxin Yang, Wei Mao, Mingqiang Huang, Hao Yu:
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge. DATE 2022: 730-735 - [c4]Peng Xue, Lunshuai Pan, Litao Sun, Mingqiang Huang:
Dual-Line-Systolic Array for High Performance CNN Accelerator. FCCM 2022: 1 - [c3]Mingqiang Huang, Yucen Liu, Quan Cheng, Shuxin Yang, Kai Li, Junyi Luo, Zhengke Yang, Qiufeng Li, Hao Yu, Changhai Man:
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. FPGA 2022: 50 - 2021
- [j1]Wei Zhang, Lunshuai Pan, Xuelong Yan, Guangchao Zhao, Hong Chen, Xingli Wang, Beng Kang Tay, Gaokuo Zhong, Jiangyu Li, Mingqiang Huang:
Hardware-Friendly Stochastic and Adaptive Learning in Memristor Convolutional Neural Networks. Adv. Intell. Syst. 3(9): 2100041 (2021) - [c2]Wenshuo Li, Hanting Chen, Mingqiang Huang, Xinghao Chen, Chunjing Xu, Yunhe Wang:
Winograd Algorithm for AdderNet. ICML 2021: 6307-6315 - [i2]Yunhe Wang, Mingqiang Huang, Kai Han, Hanting Chen, Wei Zhang, Chunjing Xu, Dacheng Tao:
AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence. CoRR abs/2101.10015 (2021) - [i1]Wenshuo Li, Hanting Chen, Mingqiang Huang, Xinghao Chen, Chunjing Xu, Yunhe Wang:
Winograd Algorithm for AdderNet. CoRR abs/2105.05530 (2021)
2010 – 2019
- 2017
- [c1]Mingqiang Huang, Xiong Xiong, Tiaoyang Li, Yanqing Wu:
High performance transistors based on two dimensional materials. ASICON 2017: 1053-1056
Coauthor Index
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