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ORCIDAn Guo 0001
Person information
- affiliation: Southeast University, Nanjing, China
Other persons with the same name
- An Guo — disambiguation page
- An Guo 0002
![[0009-0005-8661-6133]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0009-0005-8661-6133")
— Nanjing University, China - An Guo 0003 — Anyang Normal University, Anyang, China
- An Guo 0004 — Northwestern Polytechnical University, Xi'an, China
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2020 – today
- 2025
[j6]Zhaoyang Zhang, Yanqi Zhang, Feiran Liu, Zhichao Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Jun Yang, Xin Si:
A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. IEEE J. Solid State Circuits 60(3): 949-962 (2025)- [j5]An Guo, Xueshan Dong, Fangyuan Dong, Dongqi Li, Yiran Zhang, Jingmin Zhang, Jun Yang, Xin Si:
A 28 nm 128-kb Exponent- and Mantissa-Computation-In-Memory Dual-Macro for Floating-Point and INT CNNs. IEEE J. Solid State Circuits 60(10): 3639-3654 (2025) - [c13]An Guo, Jingmin Zhang, Xingyu Pu, Yi Yang, Defa Wu, Yuchen Tang, Yuhui Shi, Yinghai Gao, Zhichao Liu, Bo Wang, Tianzhu Xiong, Zhaoyang Zhang, Xi Chen, Jinwu Chen, Feiran Liu, Xing Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Xin Si, Jun Yang:
14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. ISSCC 2025: 1-3 - [c12]Xing Wang, Tianhui Jiao, Yi Yang, Shaochen Li, Dongqi Li, An Guo, Yuhui Shi, Yuchen Tang, Jinwu Chen, Zhican Zhang, Zhichao Liu, Bo Liu, Weiwei Shan, Xin Wang, Hao Cai, Wenwu Zhu, Jun Yang, Xin Si:
14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers. ISSCC 2025: 254-256 - [c11]Xi Chen, Shaochen Li, Zhican Zhang, Wentao Zheng, Xiao Tan, Yuchen Tang, Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si:
14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. ISSCC 2025: 260-262 - 2024
- [j4]An Guo, Chen Xi, Fangyuan Dong, Xingyu Pu, Dongqi Li, Jingmin Zhang, Xueshan Dong, Hui Gao, Yiran Zhang, Bo Wang, Jun Yang, Xin Si:
A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. IEEE J. Solid State Circuits 59(9): 3032-3044 (2024) - [j3]Xi Chen, Yitong Zhao, An Guo, Jinwu Chen, Fangyuan Dong, Zhaoyang Zhang, Tianzhu Xiong, Bo Wang, Yuyao Kong, Xin Si:
Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3181-3185 (2024) - [c10]An Guo, Xueshan Dong, Fangyuan Dong, Dongqi Li, Yiran Zhang, Jingmin Zhang, Yuchen Tang, Yuhui Shi, Xiao Tan, Bo Liu, Weiwei Shan, Hao Cai, Jun Yang, Xin Si:
A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. A-SSCC 2024: 1-3 - [c9]Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si:
A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. CICC 2024: 1-2 - [c8]An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si:
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. ISSCC 2024: 570-572 - 2023
- [j2]Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang:
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. Sci. China Inf. Sci. 66(10) (2023) - [c7]An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang:
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. ISSCC 2023: 128-129 - [c6]Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang:
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. ISSCC 2023: 134-135 - 2022
- [j1]An Guo, Chen Xue, Xi Chen, Xin Si:
VCCIM: a voltage coupling based computing-in-memory architecture in 28 nm for edge AI applications. CCF Trans. High Perform. Comput. 4(4): 407-420 (2022) - [c5]Xi Chen, An Guo, Xinbing Xu, Xin Si, Jun Yang:
A Quantization Model Based on a Floating-point Computing-in-Memory Architecture. APCCAS 2022: 493-496 - [c4]Zhongyuan Feng, Bo Wang, Zhaoyang Zhang, An Guo, Xin Si:
A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model. APCCAS 2022: 524-527 - [c3]An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang:
ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. ISCAS 2022: 2276-2280 - [c2]Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si:
SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. ISCAS 2022: 3383-3387 - 2021
- [c1]Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang:
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. ISOCC 2021: 195-196
Coauthor Index
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