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ORCIDXue Liu 0003
Person information
- affiliation: Northeastern University, School of Computer Science and Engineering, Shenyang, China
Other persons with the same name
- Xue Liu — disambiguation page
- Xue (Steve) Liu
![[0000-0001-5252-3442]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-5252-3442")
(aka: Xue Liu 0001) — McGill University, School of Computer Science, Montreal, QC, Canada (and 1 more) - Xue Liu 0002 — Shanghai Jiao Tong University, School of Life Sciences and Biotechnology, China
- Xue Liu 0004 — Samsung AI Center Montreal, QC, Canada
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Journal Articles
- 2021
[j7]Ze-ke Wang, Xue Liu, Kai Zhang, Haihang Zhou, Bingsheng He:
Understanding and Optimizing Conjunctive Predicates Under Memory-Efficient Storage Layouts. IEEE Trans. Knowl. Data Eng. 33(6): 2803-2817 (2021)- 2017
- [j6]Xue Liu, Ze-ke Wang, Qingxu Deng:
FPGA implementation of a reconfigurable channelization for simultaneous multichannel DRM30/FM receiver. IEEE Trans. Consumer Electron. 63(1): 1-9 (2017) - [j5]Xue Liu, Xin-Xin Yan, Ze-ke Wang, Qingxu Deng:
Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3548-3552 (2017) - 2016
- [j4]Xue Liu, Ze-ke Wang, Qing-xu Deng:
Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2449-2461 (2016) - 2015
- [j3]Ze-ke Wang, Xue Liu, Bingsheng He, Feng Yu:
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 973-977 (2015) - 2014
- [j2]Xue Liu, Qing-xu Deng, Bo-ning Hou, Ze-ke Wang:
High-speed, fixed-latency serial links with Xilinx FPGAs. J. Zhejiang Univ. Sci. C 15(2): 153-160 (2014) - 2011
- [j1]Xue Liu, Feng Yu, Ze-ke Wang:
A pipelined architecture for normal I/O order FFT. J. Zhejiang Univ. Sci. C 12(1): 76-82 (2011)
Conference and Workshop Papers
- 2020
- [c3]Jiantong Jiang, Zeke Wang, Xue Liu, Juan Gómez-Luna, Nan Guan, Qingxu Deng, Wei Zhang, Onur Mutlu:
Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs. FPGA 2020: 299-309 - 2018
- [c2]Ze-ke Wang, Kai Zhang, Haihang Zhou, Xue Liu, Bingsheng He:
Hebe: An Order-Oblivious and High-Performance Execution Scheme for Conjunctive Predicates. ICDE 2018: 1260-1263 - 2013
- [c1]Ze-ke Wang, Feng Yu, Xue Liu:
Block Processor: A resource-distributed architecture. HPEC 2013: 1-6
Coauthor Index
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