BibTeX records: Muralikrishna Balaga

download as .bib file

@inproceedings{DBLP:conf/isscc/SiauKLISVA0YANK19,
  author    = {Chang Hua Siau and
               Kwang{-}Ho Kim and
               Seungpil Lee and
               Katsuaki Isobe and
               Noboru Shibata and
               Kapil Verma and
               Takuya Ariki and
               Jason Li and
               Jong Yuh and
               Anirudh Amarnath and
               Qui Nguyen and
               Ohwon Kwon and
               Stanley Jeong and
               Heguang Li and
               Hua{-}Ling Hsu and
               Taiyuan Tseng and
               Steve Choi and
               Siddhesh Darne and
               Pradeep Anantula and
               Alex Yap and
               Hardwell Chibvongodze and
               Hitoshi Miwa and
               Minoru Yamashita and
               Mitsuyuki Watanabe and
               Koichiro Hayashi and
               Yosuke Kato and
               Toru Miwa and
               Jang Yong Kang and
               Masatoshi Okumura and
               Naoki Ookuma and
               Muralikrishna Balaga and
               Venky Ramachandra and
               Aki Matsuda and
               Swaroop Kulkarni and
               Raghavendra Rachineni and
               Pai K. Manjunath and
               Masahito Takehara and
               Anil Pai and
               Srinivas Rajendra and
               Toshiki Hisada and
               Ryo Fukuda and
               Naoya Tokiwa and
               Kazuaki Kawaguchi and
               Masashi Yamaoka and
               Hiromitsu Komai and
               Takatoshi Minamoto and
               Masaki Unno and
               Susumu Ozawa and
               Hiroshi Nakamura and
               Tomoo Hishida and
               Yasuyuki Kajitani and
               Lei Lin},
  title     = {A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s
               Write Performance Featuring Circuit-Under-Array Technology},
  booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
               San Francisco, CA, USA, February 17-21, 2019},
  pages     = {218--220},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.1109/ISSCC.2019.8662445},
  doi       = {10.1109/ISSCC.2019.8662445},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/SiauKLISVA0YANK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YamashitaMHYYMZ17,
  author    = {Ryuji Yamashita and
               Sagar Magia and
               Tsutomu Higuchi and
               Kazuhide Yoneya and
               Toshio Yamamura and
               Hiroyuki Mizukoshi and
               Shingo Zaitsu and
               Minoru Yamashita and
               Shunichi Toyama and
               Norihiro Kamae and
               Juan Lee and
               Shuo Chen and
               Jiawei Tao and
               William Mak and
               Xiaohua Zhang and
               Ying Yu and
               Yuko Utsunomiya and
               Yosuke Kato and
               Manabu Sakai and
               Masahide Matsumoto and
               Hardwell Chibvongodze and
               Naoki Ookuma and
               Hiroki Yabe and
               Subodh Taigor and
               Rangarao Samineni and
               Takuyo Kodama and
               Yoshihiko Kamata and
               Yuzuru Namai and
               Jonathan Huynh and
               Sung{-}En Wang and
               Yankang He and
               Trung Pham and
               Vivek Saraf and
               Akshay Petkar and
               Mitsuyuki Watanabe and
               Koichiro Hayashi and
               Prashant Swarnkar and
               Hitoshi Miwa and
               Aditya Pradhan and
               Sulagna Dey and
               Debasish Dwibedy and
               Thushara Xavier and
               Muralikrishna Balaga and
               Samiksha Agarwal and
               Swaroop Kulkarni and
               Zameer Papasaheb and
               Sahil Deora and
               Patrick Hong and
               Meiling Wei and
               Gopinath Balakrishnan and
               Takuya Ariki and
               Kapil Verma and
               Chang Hua Siau and
               Yingda Dong and
               Ching{-}Huang Lu and
               Toru Miwa and
               Farookh Moogat},
  title     = {11.1 {A} 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {196--197},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870328},
  doi       = {10.1109/ISSCC.2017.7870328},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/YamashitaMHYYMZ17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics