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Tao-Tao Zhu

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affiliation: Zhejiang University, Institute of VLSI Design, Hangzhou, China

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Journal Articles

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2020
[j8]
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Yan He, Zhijian Chen, Xiaoyan Xiang, Tao-Tao Zhu:
A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs. IEEE Access 8: 190251-190262 (2020)
2018
[j7]
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  - journals/ieiceee/ChenJLZXM18
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Zhijian Chen, Menghan Jia, Jiahui Luo, Tao-Tao Zhu, Xiaoyan Xiang, Jianyi Meng:
A low power QRS detection processor with adaptive scaling of processing resolution. IEICE Electron. Express 15(1): 20170882 (2018)
[j6]
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Yande Xiang, Jiahui Luo, Tao-Tao Zhu, Sheng Wang, Xiaoyan Xiang, Jianyi Meng:
ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference. IEICE Trans. Inf. Syst. 101-D(4): 1189-1198 (2018)
[j5]
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Zhijian Chen, Huanzhang Xu, Jiahui Luo, Tao-Tao Zhu, Jianyi Meng:
Low-power perceptron model based ECG processor for premature ventricular contraction detection. Microprocess. Microsystems 59: 29-36 (2018)
[j4]
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Zhijian Chen, Jiahui Luo, Kaiwen Lin, Jiaquan Wu, Tao-Tao Zhu, Xiaoyan Xiang, Jianyi Meng:
An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 948-952 (2018)
2017
[j3]
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Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. IEICE Electron. Express 14(8): 20170218 (2017)
[j2]
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Zhan-Hui Li, Tao-Tao Zhu, Zhi-Jian Chen, Jian-Yi Meng, Xiaoyan Xiang, Xiaolang Yan:
Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 670-682 (2017)
[j1]
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Tao-Tao Zhu, Jian-Yi Meng, Xiaoyan Xiang, Xiaolang Yan:
Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1681-1693 (2017)

Conference and Workshop Papers

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2015
[c1]
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Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. ASICON 2015: 1-4

Coauthor Index

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