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S. M. Mayur

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2010 – 2019

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2017
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S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI 2017: 600-603
2016
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S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of Low Power 5-Bit Hybrid Flash ADC. ISVLSI 2016: 343-348

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