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Cheeckottu Vayalil Niras

Vayalil C. Niras

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Journal Articles

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2019
[j5]
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  - journals/tcsv/NirasPK19
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Vayalil C. Niras, Manoranjan Paul, Yinan Kong:
A Residue Number System Hardware Design of Fast-Search Variable-Motion-Estimation Accelerator for HEVC/H.265. IEEE Trans. Circuits Syst. Video Technol. 29(2): 572-581 (2019)
2017
[j4]
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Cheeckottu Vayalil Niras, Yinan Kong:
VLSI Architecture of Full-Search Variable-Block-Size Motion Estimation for HEVC Video Encoding. IET Circuits Devices Syst. 11(6): 543-548 (2017)
[j3]
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Md. Selim Hossain, Yinan Kong, Ehsan Saeedi, Cheeckottu Vayalil Niras:
High-performance elliptic curve cryptography processor over NIST prime fields. IET Comput. Digit. Tech. 11(1): 33-42 (2017)
2016
[j2]
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Cheeckottu Vayalil Niras, Yinan Kong:
Fast sign-detection algorithm for residue number system moduli set {2ⁿ - 1, 2ⁿ, 2ⁿ⁺¹ - 1}. IET Comput. Digit. Tech. 10(2): 54-58 (2016)
[j1]
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Azadeh Safari, Cheeckottu Vayalil Niras, Yinan Kong:
Power-performance enhancement of two-dimensional RNS-based DWT image processor using static voltage scaling. Integr. 53: 145-156 (2016)

Conference and Workshop Papers

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2017
[c3]
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  - conf/icip/VayalilPK17
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Cheeckottu Vayalil Niras, Manoranjan Paul, Yinan Kong:
A novel angle-restricted test zone search algorithm for performance improvement of HEVC. ICIP 2017: 6-10
2016
[c2]
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  - conf/ems/NirasHK16
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Cheeckottu Vayalil Niras, Joshua Haddrill, Yinan Kong:
An Efficient ASIC Design of Variable-Length Discrete Cosine Transform for HEVC. EMS 2016: 229-233
2014
[c1]
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  - conf/isicir/KongSN14
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Yinan Kong, Azadeh Safari, Cheeckottu Vayalil Niras:
A low-cost architecture for DWT filter banks in RNS applications. ISIC 2014: 448-451

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