BibTeX records: Chung-Wei Hsu

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@inproceedings{DBLP:conf/iscas/LienHC21,
  author    = {Hong{-}Han Lien and
               Chung{-}Wei Hsu and
               Tian{-}Sheuan Chang},
  title     = {{VSA:} Reconfigurable Vectorwise Spiking Neural Network Accelerator},
  booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
               Daegu, South Korea, May 22-28, 2021},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2021},
  url       = {https://doi.org/10.1109/ISCAS51556.2021.9401181},
  doi       = {10.1109/ISCAS51556.2021.9401181},
  timestamp = {Fri, 02 Jul 2021 12:26:54 +0200},
  biburl    = {https://dblp.org/rec/conf/iscas/LienHC21.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/HsuCHCSHTKH18,
  author    = {Chung{-}Wei Hsu and
               Soon{-}Jyh Chang and
               Chun{-}Po Huang and
               Li{-}Jen Chang and
               Ya{-}Ting Shyu and
               Chih{-}Huei Hou and
               Hwa{-}An Tseng and
               Chih{-}Yuan Kung and
               Huan{-}Jui Hu},
  title     = {A 12-b 40-MS/s Calibration-Free {SAR} {ADC}},
  journal   = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume    = {65-I},
  number    = {3},
  pages     = {881--890},
  year      = {2018},
  url       = {https://doi.org/10.1109/TCSI.2017.2771364},
  doi       = {10.1109/TCSI.2017.2771364},
  timestamp = {Fri, 22 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/tcas/HsuCHCSHTKH18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HsuCHC17,
  author    = {Chung{-}Wei Hsu and
               Li{-}Jen Chang and
               Chun{-}Po Huang and
               Soon{-}Jyh Chang},
  title     = {A 12-bit 40-MS/s calibration-free {SAR} {ADC}},
  booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
               Baltimore, MD, USA, May 28-31, 2017},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://doi.org/10.1109/ISCAS.2017.8050307},
  doi       = {10.1109/ISCAS.2017.8050307},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/iscas/HsuCHC17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/HudecHWLCWFHLH16,
  author    = {Boris Hudec and
               Chung{-}Wei Hsu and
               I{-}Ting Wang and
               Wei{-}Li Lai and
               Che{-}Chia Chang and
               Taifang Wang and
               Karol Fr{\"{o}}hlich and
               Chia{-}Hua Ho and
               Chen{-}Hsi Lin and
               Tuo{-}Hung Hou},
  title     = {3D resistive {RAM} cell design for high-density storage class memory
               - a review},
  journal   = {Sci. China Inf. Sci.},
  volume    = {59},
  number    = {6},
  pages     = {061403:1--061403:21},
  year      = {2016},
  url       = {https://doi.org/10.1007/s11432-016-5566-0},
  doi       = {10.1007/s11432-016-5566-0},
  timestamp = {Mon, 02 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/chinaf/HudecHWLCWFHLH16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mr/ChouHHLCH15,
  author    = {Chun{-}Tse Chou and
               Boris Hudec and
               Chung{-}Wei Hsu and
               Wei{-}Li Lai and
               Chih{-}Cheng Chang and
               Tuo{-}Hung Hou},
  title     = {Crossbar array of selector-less TaO\({}_{\mbox{x}}\)/TiO\({}_{\mbox{2}}\)
               bilayer {RRAM}},
  journal   = {Microelectron. Reliab.},
  volume    = {55},
  number    = {11},
  pages     = {2220--2223},
  year      = {2015},
  url       = {https://doi.org/10.1016/j.microrel.2015.04.002},
  doi       = {10.1016/j.microrel.2015.04.002},
  timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/mr/ChouHHLCH15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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