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C. Arun
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2020 – today
- 2023
- [j9]C. Arun
, C. Lakshmi:
Performance evaluation of oversampling algorithm: MAHAKIL using ensemble classifiers. Int. J. Bus. Intell. Data Min. 22(1/2): 1-15 (2023) - 2022
- [j8]C. Saravanakumar, R. Priscilla, B. Prabha
, A. Kavitha, M. Prakash, C. Arun:
An Efficient On-Demand Virtual Machine Migration in Cloud Using Common Deployment Model. Comput. Syst. Sci. Eng. 42(1): 245-256 (2022) - [j7]C. Arun
, C. Lakshmi:
Genetic algorithm-based oversampling approach to prune the class imbalance issue in software defect prediction. Soft Comput. 26(23): 12915-12931 (2022) - 2020
- [j6]C. Arun, K. Prabu:
A multi-objective EBCO-TS algorithm for efficient task scheduling in mobile cloud computing. Int. J. Netw. Virtual Organisations 22(4): 366-386 (2020)
2010 – 2019
- 2018
- [j5]Gobalakrishnan Natesan
, C. Arun:
A New Multi-Objective Optimal Programming Model for Task Scheduling using Genetic Gray Wolf Optimization in Cloud Computing. Comput. J. 61(10): 1523-1536 (2018) - 2016
- [j4]C. Saravanakumar, C. Arun:
Efficient Idle Virtual Machine Management for Heterogeneous Cloud using Common Deployment Model. KSII Trans. Internet Inf. Syst. 10(4): 1501-1518 (2016) - 2011
- [j3]Periyathambi Ezhumalai, A. Chilambuchelvan, C. Arun:
Novel NoC Topology Construction for High-Performance Communications. J. Comput. Networks Commun. 2011: 405697:1-405697:6 (2011) - 2010
- [i1]Periyathambi Ezhumalai, S. Manojkumar, C. Arun, P. Sakthivel, D. Sridharan:
High Performance Hybrid Two Layer Router Architecture for FPGAs Using Network On Chip. CoRR abs/1002.2420 (2010)
2000 – 2009
- 2009
- [j2]C. Arun, V. Rajamani:
A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering. Int. J. Commun. Netw. Syst. Sci. 2(6): 575-582 (2009) - 2008
- [c2]N. Ashokraj, C. Arun, K. Murugan:
Route Cache Optimization Mechanism Using Smart Packets for On-demand Routing Procotol in MANET. ICIT 2008: 141-146 - [c1]C. Arun, V. Rajamani:
Design and VLSI implementation of a Low Probability of Error Viterbi Decoder. ICETET 2008: 418-423 - 2007
- [j1]C. Arun, V. Rajamani:
Minimized Memory Architecture for Low Latency Viterbi Decoder Using Zig-Zag Algorithm. Int. J. Wirel. Opt. Commun. 4(3): 313-323 (2007)
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