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David Rennie
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2010 – 2019
- 2012
- [j3]David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Richard Wong:
Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1626-1634 (2012) - 2011
- [c5]David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong:
Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. CICC 2011: 1-4 - [c4]David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev:
Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops. ISQED 2011: 583-590
2000 – 2009
- 2009
- [j2]Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev:
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC. IEEE J. Solid State Circuits 44(9): 2543-2553 (2009) - 2008
- [j1]David Rennie, Manoj Sachdev:
A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(3): 796-803 (2008) - 2007
- [b1]David J. Rennie:
Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits. University of Waterloo, Ontario, Canada, 2007 - [c3]David Rennie, Manoj Sachdev:
A Novel Tri-State Binary Phase Detector. ISCAS 2007: 185-188 - [c2]Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner
, Kenneth Ikeda, Gell Gellman, Tanay Karnik:
Low Voltage Buffered Bandgap Reference. ISQED 2007: 93-97 - [c1]David Rennie, Manoj Sachdev:
Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits. ISQED 2007: 305-310
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