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Sucheta Mohapatra

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affiliation: Portland State University, OR, USA

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Journal Articles

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2021
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Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske:
Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 271-275 (2021)

Conference and Workshop Papers

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2016
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Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
Buffered Interconnects in 3D IC Layout Design. SLIP 2016: 4:1-4:8
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Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
Performance optimization and power efficiency in 3D IC with buffer insertion scheme. SoCC 2016: 229-234
2015
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Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
Dynamic nets-to-TSVs assignment in 3D floorplanning. ISCAS 2015: 1870-1873
2014
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Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
3D floorplanning with nets-to-TSVs assignment. ICECS 2014: 578-581

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