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ORCIDSwapnil Mhaske
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2010 – 2019
- 2019
[i3]Swapnil Mhaske, Predrag Spasojevic, Ahsan Aziz:
A Blockage Model for the Open Area Mm-wave Device-to-Device Environment. CoRR abs/1909.12992 (2019)- 2017
- [j1]Swapnil Mhaske
, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis. Int. J. Reconfigurable Comput. 2017: 3689308:1-3689308:23 (2017) - 2016
- [c6]Swapnil Mhaske, Predrag Spasojevic, Ahsan Aziz, Malik Muhammad Usman Gul:
Link quality analysis in the presence of blockages for analog beamformed mm-wave channel. MILCOM 2016: 219-224 - [c5]Swapnil Mhaske, Hojin Kee, Tai Ly, Predrag Spasojevic:
FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis. Sarnoff Symposium 2016: 19-21 - 2015
- [c4]Brennan Young, Swapnil Mhaske, Predrag Spasojevic:
Rate compatible IRA codes using row splitting for 5G wireless. CISS 2015: 1-5 - [c3]Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation. Sarnoff Symposium 2015: 88-93 - [c2]Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
High-Throughput FPGA-Based QC-LDPC Decoder Architecture. VTC Fall 2015: 1-5 - [i2]Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
High-Throughput FPGA-based QC-LDPC Decoder Architecture. CoRR abs/1503.02986 (2015) - [i1]Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R. CoRR abs/1505.04339 (2015) - 2014
- [c1]Hojin Kee, Swapnil Mhaske, David Uliana, Adam Arnesen, Newton Petersen, Taylor L. Riché, Dustyn Blasig, Tai Ly:
Rapid and high-level constraint-driven prototyping using lab VIEW FPGA. GlobalSIP 2014: 45-49
Coauthor Index
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