BibTeX records: Prashant J. Nair

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@inproceedings{DBLP:conf/dsn/NairAQ19,
  author    = {Prashant J. Nair and
               Bahar Asgari and
               Moinuddin K. Qureshi},
  title     = {SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable
               {STTRAM}},
  booktitle = {49th Annual {IEEE/IFIP} International Conference on Dependable Systems
               and Networks, {DSN} 2019, Portland, OR, USA, June 24-27, 2019},
  pages     = {388--400},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.1109/DSN.2019.00048},
  doi       = {10.1109/DSN.2019.00048},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/dsn/NairAQ19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/0005TNQ19,
  author    = {Poulami Das and
               Swamit S. Tannu and
               Prashant J. Nair and
               Moinuddin K. Qureshi},
  title     = {A Case for Multi-Programming Quantum Computers},
  booktitle = {Proceedings of the 52nd Annual {IEEE/ACM} International Symposium
               on Microarchitecture, {MICRO} 2019, Columbus, OH, USA, October 12-16,
               2019},
  pages     = {291--303},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3352460.3358287},
  doi       = {10.1145/3352460.3358287},
  timestamp = {Wed, 16 Oct 2019 09:55:30 +0200},
  biburl    = {https://dblp.org/rec/conf/micro/0005TNQ19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/HongABHN19,
  author    = {Seokin Hong and
               B{\"{u}}lent Abali and
               Alper Buyuktosunoglu and
               Michael B. Healy and
               Prashant J. Nair},
  title     = {Touch{\'{e}}: Towards Ideal and Efficient Cache Compression By
               Mitigating Tag Area Overheads},
  booktitle = {Proceedings of the 52nd Annual {IEEE/ACM} International Symposium
               on Microarchitecture, {MICRO} 2019, Columbus, OH, USA, October 12-16,
               2019},
  pages     = {453--465},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3352460.3358281},
  doi       = {10.1145/3352460.3358281},
  timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/micro/HongABHN19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1909-00553,
  author    = {Seokin Hong and
               B{\"{u}}lent Abali and
               Alper Buyuktosunoglu and
               Michael B. Healy and
               Prashant J. Nair},
  title     = {Touch{\'{e}}: Towards Ideal and Efficient Cache Compression By
               Mitigating Tag Area Overheads},
  journal   = {CoRR},
  volume    = {abs/1909.00553},
  year      = {2019},
  url       = {http://arxiv.org/abs/1909.00553},
  archivePrefix = {arXiv},
  eprint    = {1909.00553},
  timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/corr/abs-1909-00553.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/SaileshwarNREQ18,
  author    = {Gururaj Saileshwar and
               Prashant J. Nair and
               Prakash Ramrakhyani and
               Wendy Elsasser and
               Moinuddin K. Qureshi},
  title     = {{SYNERGY:} Rethinking Secure-Memory Design for Error-Correcting Memories},
  booktitle = {{IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2018, Vienna, Austria, February 24-28, 2018},
  pages     = {454--465},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {https://doi.org/10.1109/HPCA.2018.00046},
  doi       = {10.1109/HPCA.2018.00046},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/conf/hpca/SaileshwarNREQ18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/HongNABKH18,
  author    = {Seokin Hong and
               Prashant Jayaprakash Nair and
               B{\"{u}}lent Abali and
               Alper Buyuktosunoglu and
               Kyu{-}hyoun Kim and
               Michael B. Healy},
  title     = {Attach{\'{e}}: Towards Ideal Memory Compression by Mitigating
               Metadata Bandwidth Overheads},
  booktitle = {51st Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2018, Fukuoka, Japan, October 20-24, 2018},
  pages     = {326--338},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {https://doi.org/10.1109/MICRO.2018.00034},
  doi       = {10.1109/MICRO.2018.00034},
  timestamp = {Thu, 13 Feb 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/micro/HongNABKH18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/SaileshwarNREJQ18,
  author    = {Gururaj Saileshwar and
               Prashant J. Nair and
               Prakash Ramrakhyani and
               Wendy Elsasser and
               Jos{\'{e}} A. Joao and
               Moinuddin K. Qureshi},
  title     = {Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead
               Secure Memories},
  booktitle = {51st Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2018, Fukuoka, Japan, October 20-24, 2018},
  pages     = {416--427},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {https://doi.org/10.1109/MICRO.2018.00041},
  doi       = {10.1109/MICRO.2018.00041},
  timestamp = {Fri, 24 Jan 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/micro/SaileshwarNREJQ18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1805-03184,
  author    = {Kevin K. Chang and
               Prashant J. Nair and
               Saugata Ghose and
               Donghyuk Lee and
               Moinuddin K. Qureshi and
               Onur Mutlu},
  title     = {{LISA:} Increasing Internal Connectivity in {DRAM} for Fast Data Movement
               and Low Latency},
  journal   = {CoRR},
  volume    = {abs/1805.03184},
  year      = {2018},
  url       = {http://arxiv.org/abs/1805.03184},
  archivePrefix = {arXiv},
  eprint    = {1805.03184},
  timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/corr/abs-1805-03184.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/YoungNQ17,
  author    = {Vinson Young and
               Prashant J. Nair and
               Moinuddin K. Qureshi},
  title     = {{DICE:} Compressing {DRAM} Caches for Bandwidth and Capacity},
  booktitle = {Proceedings of the 44th Annual International Symposium on Computer
               Architecture, {ISCA} 2017, Toronto, ON, Canada, June 24-28, 2017},
  pages     = {627--638},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://dl.acm.org/citation.cfm?id=3080243},
  timestamp = {Mon, 26 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/isca/YoungNQ17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/TannuMNCQ17,
  author    = {Swamit S. Tannu and
               Zachary A. Myers and
               Prashant J. Nair and
               Douglas M. Carmean and
               Moinuddin K. Qureshi},
  editor    = {Hillery C. Hunter and
               Jaime Moreno and
               Joel S. Emer and
               Daniel S{\'{a}}nchez},
  title     = {Taming the instruction bandwidth of quantum computers via hardware-managed
               error correction},
  booktitle = {Proceedings of the 50th Annual {IEEE/ACM} International Symposium
               on Microarchitecture, {MICRO} 2017, Cambridge, MA, USA, October 14-18,
               2017},
  pages     = {679--691},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3123939.3123940},
  doi       = {10.1145/3123939.3123940},
  timestamp = {Mon, 16 Dec 2019 13:26:25 +0100},
  biburl    = {https://dblp.org/rec/conf/micro/TannuMNCQ17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/Nair17,
  author    = {Prashant J. Nair},
  title     = {Architectural Techniques to Enable Reliable and Scalable Memory Systems},
  journal   = {CoRR},
  volume    = {abs/1704.03991},
  year      = {2017},
  url       = {http://arxiv.org/abs/1704.03991},
  archivePrefix = {arXiv},
  eprint    = {1704.03991},
  timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/corr/Nair17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/NairRQ16,
  author    = {Prashant J. Nair and
               David A. Roberts and
               Moinuddin K. Qureshi},
  title     = {FaultSim: {A} Fast, Configurable Memory-Reliability Simulator for
               Conventional and 3D-Stacked Systems},
  journal   = {{ACM} Trans. Archit. Code Optim.},
  volume    = {12},
  number    = {4},
  pages     = {44:1--44:24},
  year      = {2016},
  url       = {https://doi.org/10.1145/2831234},
  doi       = {10.1145/2831234},
  timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/taco/NairRQ16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/NairRQ16a,
  author    = {Prashant J. Nair and
               David A. Roberts and
               Moinuddin K. Qureshi},
  title     = {Citadel: Efficiently Protecting Stacked Memory from {TSV} and Large
               Granularity Failures},
  journal   = {{ACM} Trans. Archit. Code Optim.},
  volume    = {12},
  number    = {4},
  pages     = {49:1--49:24},
  year      = {2016},
  url       = {https://doi.org/10.1145/2840807},
  doi       = {10.1145/2840807},
  timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/taco/NairRQ16a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/ChangNLGQM16,
  author    = {Kevin K. Chang and
               Prashant J. Nair and
               Donghyuk Lee and
               Saugata Ghose and
               Moinuddin K. Qureshi and
               Onur Mutlu},
  title     = {Low-Cost Inter-Linked Subarrays {(LISA):} Enabling fast inter-subarray
               data movement in {DRAM}},
  booktitle = {2016 {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2016, Barcelona, Spain, March 12-16, 2016},
  pages     = {568--580},
  publisher = {{IEEE} Computer Society},
  year      = {2016},
  url       = {https://doi.org/10.1109/HPCA.2016.7446095},
  doi       = {10.1109/HPCA.2016.7446095},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/conf/hpca/ChangNLGQM16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/NairSQ16,
  author    = {Prashant J. Nair and
               Vilas Sridharan and
               Moinuddin K. Qureshi},
  title     = {{XED:} Exposing On-Die Error Detection Information for Strong Memory
               Reliability},
  booktitle = {43rd {ACM/IEEE} Annual International Symposium on Computer Architecture,
               {ISCA} 2016, Seoul, South Korea, June 18-22, 2016},
  pages     = {341--353},
  publisher = {{IEEE} Computer Society},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISCA.2016.38},
  doi       = {10.1109/ISCA.2016.38},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/isca/NairSQ16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/KimNQ15,
  author    = {Dae{-}Hyun Kim and
               Prashant J. Nair and
               Moinuddin K. Qureshi},
  title     = {Architectural Support for Mitigating Row Hammering in {DRAM} Memories},
  journal   = {{IEEE} Comput. Archit. Lett.},
  volume    = {14},
  number    = {1},
  pages     = {9--12},
  year      = {2015},
  url       = {https://doi.org/10.1109/LCA.2014.2332177},
  doi       = {10.1109/LCA.2014.2332177},
  timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/cal/KimNQ15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/YoungNQ15,
  author    = {Vinson Young and
               Prashant J. Nair and
               Moinuddin K. Qureshi},
  editor    = {{\"{O}}zcan {\"{O}}zturk and
               Kemal Ebcioglu and
               Sandhya Dwarkadas},
  title     = {{DEUCE:} Write-Efficient Encryption for Non-Volatile Memories},
  booktitle = {Proceedings of the Twentieth International Conference on Architectural
               Support for Programming Languages and Operating Systems, {ASPLOS}
               '15, Istanbul, Turkey, March 14-18, 2015},
  pages     = {33--44},
  publisher = {{ACM}},
  year      = {2015},
  url       = {https://doi.org/10.1145/2694344.2694387},
  doi       = {10.1145/2694344.2694387},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/asplos/YoungNQ15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsn/ChouNQ15,
  author    = {Chia{-}Chen Chou and
               Prashant J. Nair and
               Moinuddin K. Qureshi},
  title     = {Reducing Refresh Power in Mobile Devices with Morphable {ECC}},
  booktitle = {45th Annual {IEEE/IFIP} International Conference on Dependable Systems
               and Networks, {DSN} 2015, Rio de Janeiro, Brazil, June 22-25, 2015},
  pages     = {355--366},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/DSN.2015.33},
  doi       = {10.1109/DSN.2015.33},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/dsn/ChouNQ15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsn/QureshiKKNM15,
  author    = {Moinuddin K. Qureshi and
               Dae{-}Hyun Kim and
               Samira Manabi Khan and
               Prashant J. Nair and
               Onur Mutlu},
  title     = {{AVATAR:} {A} Variable-Retention-Time {(VRT)} Aware Refresh for {DRAM}
               Systems},
  booktitle = {45th Annual {IEEE/IFIP} International Conference on Dependable Systems
               and Networks, {DSN} 2015, Rio de Janeiro, Brazil, June 22-25, 2015},
  pages     = {427--437},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/DSN.2015.58},
  doi       = {10.1109/DSN.2015.58},
  timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/dsn/QureshiKKNM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/NairCRQ15,
  author    = {Prashant J. Nair and
               Chia{-}Chen Chou and
               Bipin Rajendran and
               Moinuddin K. Qureshi},
  title     = {Reducing read latency of phase change memory via early read and Turbo
               Read},
  booktitle = {21st {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2015, Burlingame, CA, USA, February 7-11, 2015},
  pages     = {309--319},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/HPCA.2015.7056042},
  doi       = {10.1109/HPCA.2015.7056042},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/conf/hpca/NairCRQ15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/NairCQ14,
  author    = {Prashant J. Nair and
               Chia{-}Chen Chou and
               Moinuddin K. Qureshi},
  title     = {Refresh pausing in {DRAM} memory systems},
  journal   = {{ACM} Trans. Archit. Code Optim.},
  volume    = {11},
  number    = {1},
  pages     = {10:1--10:26},
  year      = {2014},
  url       = {https://doi.org/10.1145/2579669},
  doi       = {10.1145/2579669},
  timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/taco/NairCQ14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/NairRQ14,
  author    = {Prashant J. Nair and
               David A. Roberts and
               Moinuddin K. Qureshi},
  title     = {Citadel: Efficiently Protecting Stacked Memory from Large Granularity
               Failures},
  booktitle = {47th Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2014, Cambridge, United Kingdom, December 13-17, 2014},
  pages     = {51--62},
  publisher = {{IEEE} Computer Society},
  year      = {2014},
  url       = {https://doi.org/10.1109/MICRO.2014.57},
  doi       = {10.1109/MICRO.2014.57},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/micro/NairRQ14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/NairCQ13,
  author    = {Prashant J. Nair and
               Chia{-}Chen Chou and
               Moinuddin K. Qureshi},
  title     = {A case for Refresh Pausing in {DRAM} memory systems},
  booktitle = {19th {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2013, Shenzhen, China, February 23-27, 2013},
  pages     = {627--638},
  publisher = {{IEEE} Computer Society},
  year      = {2013},
  url       = {https://doi.org/10.1109/HPCA.2013.6522355},
  doi       = {10.1109/HPCA.2013.6522355},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/conf/hpca/NairCQ13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/NairKQ13,
  author    = {Prashant J. Nair and
               Dae{-}Hyun Kim and
               Moinuddin K. Qureshi},
  editor    = {Avi Mendelson},
  title     = {ArchShield: architectural framework for assisting {DRAM} scaling by
               tolerating high error rates},
  booktitle = {The 40th Annual International Symposium on Computer Architecture,
               ISCA'13, Tel-Aviv, Israel, June 23-27, 2013},
  pages     = {72--83},
  publisher = {{ACM}},
  year      = {2013},
  url       = {https://doi.org/10.1145/2485922.2485929},
  doi       = {10.1145/2485922.2485929},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/isca/NairKQ13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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