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ORCIDAkhil Garg 0001
Person information
- affiliation: Cadence Design Systems, Noida, India
- affiliation (former): STMicroelectronics India, Greater Noida, India
Other persons with the same name
- Akhil Garg 0002
![[0000-0001-5731-4105]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-5731-4105")
— Huazhong University of Science and Technology, State Key Laboratory of Digital Manufacturing Equipment and Technology, Wuhan, China (and 2 more) - Akhil Garg 0003 — Indian Institute of Technology Delhi, Centre for Automotive Research and Tribology, India
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Journal Articles
- 2010
[j1]Prashant Dubey, Akhil Garg, Shashank Mahajan:
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time. J. Electron. Test. 26(6): 659-666 (2010)
Conference and Workshop Papers
- 2014
- [c10]Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen:
Efficient testing of hierarchical core-based SOCs. ITC 2014: 1-10 - 2013
- [c9]Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj:
SmartScan - Hierarchical test compression for pin-limited low power designs. ITC 2013: 1-9 - 2011
- [c8]Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto:
State of the art low capture power methodology. ITC 2011: 1-10 - 2008
- [c7]Akhil Garg, Prashant Dubey:
On Chip Jitter Measurement through a High Accuracy TDC. ISQED 2008: 844-847 - [c6]Swapnil Bahl, Rajiv Sarkar, Akhil Garg:
Low Power Test. ITC 2008: 1 - 2007
- [c5]Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani:
Built in Defect Prognosis for Embedded Memories. DDECS 2007: 167-172 - [c4]Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani:
GALS Based Shared Test Architecture for Embedded Memories. ISCAS 2007: 157-160 - [c3]Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani:
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. ISVLSI 2007: 171-178 - 2006
- [c2]Akhil Garg, Prashant Dubey:
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. DFT 2006: 166-174 - [c1]Akhil Garg, Prashant Dubey:
Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost. SoCC 2006: 235-238
Coauthor Index
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