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Mummaneni Kavicharan

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affiliation: National Institute of Technology Warangal, India

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Journal Articles

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2016
[j3]
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Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao, Addanki Prathima:
Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects. Circuits Syst. Signal Process. 35(9): 3049-3065 (2016)
2015
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Nukala Suryanarayana Murthy, Mummaneni Kavicharan:
A Survey on FDTD-Based Interconnect Modeling. J. Circuits Syst. Comput. 24(1): 1530001:1-1530001:32 (2015)
2014
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Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao:
Efficient delay and Crosstalk estimation Models for Current-mode High Speed interconnects under Ramp input. J. Circuits Syst. Comput. 23(6) (2014)

Conference and Workshop Papers

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2013
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Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao:
An efficient delay estimation model for high speed VLSI interconnects. ICACCI 2013: 1358-1362

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