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2020 – today
- 2021
[c10]Pawel Kwiatkowski, Dominik Sondej
, Ryszard Szplet:
A brief review of wave union TDCs. EBCCSP 2021: 1-6- 2020
- [j6]Pawel Kwiatkowski, Ryszard Szplet:
Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device. IEEE Trans. Instrum. Meas. 69(10): 7353-7364 (2020) - [c9]Pawel Kwiatkowski, Ryszard Szplet:
Multisampling wave union time-to-digital converter. EBCCSP 2020: 1-5
2010 – 2019
- 2019
- [j5]Ryszard Szplet, Rafal Szymanowski, Dominik Sondej:
Measurement Uncertainty of Precise Interpolating Time Counters. IEEE Trans. Instrum. Meas. 68(11): 4348-4356 (2019) - [c8]Pawel Kwiatkowski, Ryszard Szplet:
Time-to-Digital Converter with Pseudo-Segmented Delay Line. I2MTC 2019: 1-6 - [c7]Ryszard Szplet, Slawomir Jarzynski:
A 9 ps time interval digitizer based on pulse repetition and averaging. I2MTC 2019: 1-5 - 2018
- [c6]Pawel Kwiatkowski, Ryszard Szplet:
Digital-to-time converter with pulse train generation capability. I2MTC 2018: 1-6 - 2017
- [c5]Ryszard Szplet, Pawel Kwiatkowski, Zbigniew Jachna, Krzysztof Rozyc:
Four-channel, precise, time-event recorder in programmable device. EBCCSP 2017: 1-5 - 2016
- [j4]Ryszard Szplet, Dominik Sondej, Grzegorz Grzeda:
High-Precision Time Digitizer Based on Multiedge Coding in Independent Coding Lines. IEEE Trans. Instrum. Meas. 65(8): 1884-1894 (2016) - [j3]Ryszard Szplet, Pawel Kwiatkowski, Zbigniew Jachna, Krzysztof Rozyc:
An Eight-Channel 4.5-ps Precision Timestamps-Based Time Interval Counter in FPGA Chip. IEEE Trans. Instrum. Meas. 65(9): 2088-2100 (2016) - [c4]Pawel Kwiatkowski, Ryszard Szplet, Zbigniew Jachna, Krzysztof Rozyc:
A time digitizer based on multiphase clock implemented in FPGA device. EBCCSP 2016: 1-6 - 2015
- [c3]Dominik Sondej, Ryszard Szplet:
A comparison of methods for time-to-digital conversion based on independent coding lines and multi-edge coding. MIXDES 2015: 243-247 - 2014
- [c2]Dominik Sondej, Ryszard Szplet:
A combination of multi-edge coding and independent coding lines for time-to-digital conversion. FPL 2014: 1-2 - [c1]Ryszard Szplet, Dominik Sondej, Grzegorz Grzeda:
Subpicosecond-resolution time-to-digital converter with multi-edge coding in independent coding lines. I2MTC 2014: 747-751 - 2010
- [j2]Ryszard Szplet, Kamil Klepacki:
An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking. IEEE Trans. Instrum. Meas. 59(6): 1663-1670 (2010)
2000 – 2009
- 2000
- [j1]Ryszard Szplet, Józef Kalisz, Rafal Szymanowski:
Interpolating time counter with 100 ps resolution on a single FPGA device. IEEE Trans. Instrum. Meas. 49(4): 879-883 (2000)
Coauthor Index
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