BibTeX records: Satoru Takase

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@article{DBLP:journals/jssc/LiuYSCLBYZYOSACGHKLMNPPSWYNTHMGTYOOTIF14,
  author    = {Tz{-}Yi Liu and
               Tian Hong Yan and
               Roy Scheuerlein and
               Yingchang Chen and
               Jeffrey KoonYee Lee and
               Gopinath Balakrishnan and
               Gordon Yee and
               Henry Zhang and
               Alex Yap and
               Jingwen Ouyang and
               Takahiko Sasaki and
               Ali Al{-}Shamma and
               Chin{-}Yu Chen and
               Mayank Gupta and
               Greg Hilton and
               Achal Kathuria and
               Vincent Lai and
               Masahide Matsumoto and
               Anurag Nigam and
               Anil Pai and
               Jayesh Pakhale and
               Chang Hua Siau and
               Xiaoxia Wu and
               Yibo Yin and
               Nicolas Nagel and
               Yoichiro Tanaka and
               Masaaki Higashitani and
               Tim Minvielle and
               Chandu Gorla and
               Takayuki Tsukamoto and
               Takeshi Yamaguchi and
               Mutsumi Okajima and
               Takayuki Okamura and
               Satoru Takase and
               Hirofumi Inoue and
               Luca Fasoli},
  title     = {A 130.7-mm\({}^{\mbox{2}}\) 2-Layer 32-Gb ReRAM Memory Device in 24-nm
               Technology},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {49},
  number    = {1},
  pages     = {140--153},
  year      = {2014},
  url       = {https://doi.org/10.1109/JSSC.2013.2280296},
  doi       = {10.1109/JSSC.2013.2280296},
  timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/LiuYSCLBYZYOSACGHKLMNPPSWYNTHMGTYOOTIF14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LiuYSCLBYZYOSAACGHJKLMMNPPSWYPKHWNTHMGTYOOTHIFMSQ13,
  author    = {Tz{-}Yi Liu and
               Tian Hong Yan and
               Roy Scheuerlein and
               Yingchang Chen and
               Jeffrey KoonYee Lee and
               Gopinath Balakrishnan and
               Gordon Yee and
               Henry Zhang and
               Alex Yap and
               Jingwen Ouyang and
               Takahiko Sasaki and
               Sravanti Addepalli and
               Ali Al{-}Shamma and
               Chin{-}Yu Chen and
               Mayank Gupta and
               Greg Hilton and
               Saurabh Joshi and
               Achal Kathuria and
               Vincent Lai and
               Deep Masiwal and
               Masahide Matsumoto and
               Anurag Nigam and
               Anil Pai and
               Jayesh Pakhale and
               Chang Hua Siau and
               Xiaoxia Wu and
               Ronald Yin and
               Liping Peng and
               Jang Yong Kang and
               Sharon Huynh and
               Huijuan Wang and
               Nicolas Nagel and
               Yoichiro Tanaka and
               Masaaki Higashitani and
               Tim Minvielle and
               Chandu Gorla and
               Takayuki Tsukamoto and
               Takeshi Yamaguchi and
               Mutsumi Okajima and
               Takayuki Okamura and
               Satoru Takase and
               Takahiko Hara and
               Hirofumi Inoue and
               Luca Fasoli and
               Mehrdad Mofidi and
               Ritu Shrivastava and
               Khandker Quader},
  title     = {A 130.7mm\({}^{\mbox{2}}\) 2-layer 32Gb ReRAM memory device in 24nm
               technology},
  booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
               of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
               17-21, 2013},
  pages     = {210--211},
  publisher = {{IEEE}},
  year      = {2013},
  url       = {https://doi.org/10.1109/ISSCC.2013.6487703},
  doi       = {10.1109/ISSCC.2013.6487703},
  timestamp = {Mon, 10 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/LiuYSCLBYZYOSAACGHJKLMMNPPSWYPKHWNTHMGTYOOTHIFMSQ13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/TakaseK99,
  author    = {Satoru Takase and
               Natsuki Kushiyama},
  title     = {A 1.6-GByte/s {DRAM} with flexible mapping redundancy technique and
               additional refresh scheme},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {34},
  number    = {11},
  pages     = {1600--1606},
  year      = {1999},
  url       = {https://doi.org/10.1109/4.799868},
  doi       = {10.1109/4.799868},
  timestamp = {Tue, 05 Jul 2022 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/TakaseK99.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}