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Chien-Jian Tseng

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Journal Articles

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2014
[j3]
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Chien-Jian Tseng, Chieh-Fan Lai, Hsin-Shu Chen:
A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2805-2815 (2014)
2013
[j2]
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Chien-Jian Tseng, Yi-Chun Hsieh, Ching-Hua Yang, Hsin-Shu Chen:
A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2902-2910 (2013)
2012
[j1]
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Chien-Jian Tseng, Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, Hsin-Shu Chen:
A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC. IEEE J. Solid State Circuits 47(6): 1334-1343 (2012)

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