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2010 – 2019
- 2015
[c7]Chitra Natarajan, Carl J. Beckmann, Anthony Nguyen, Mauricio Araya-Polo, Tryggve Fossum, Detlef Hohl:
Simulating stencil-based application on future Xeon Phi processor. PMBS@SC 2015: 7:1-7:10- 2013
- [j1]Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer:
Using in-flight chains to build a scalable cache coherence protocol. ACM Trans. Archit. Code Optim. 10(4): 28:1-28:24 (2013) - 2011
- [r1]Joel S. Emer, Tryggve Fossum:
DEC Alpha. Encyclopedia of Parallel Computing 2011: 535-545
2000 – 2009
- 2008
- [c6]Tryggve Fossum:
Multi Core Design for Chip Level Multiprocessing. LASER Summer School 2008: 162-187 - 2007
- [c5]Tryggve Fossum:
On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing. Hot Interconnects 2007: 4 - 2004
- [c4]Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt:
Cache Scrubbing in Microprocessors: Myth or Necessity? PRDC 2004: 37-42
1990 – 1999
- 1990
- [c3]Tryggve Fossum, David B. Fite:
Designing a VAX for high performance. Compcon 1990: 36-43
1980 – 1989
- 1985
- [c2]Fernando C. Colón Osorio, Tryggve Fossum, William Hilliard, William Brucket, Paul Guglielmo, John Bloem:
The Microarchitecture of the VAX 8600. COMPCON 1985: 175 - [c1]Tryggve Fossum, William J. Grundmann, Virginia Blaha:
Floating Point Processor for the VAX 8600. COMPCON 1985: 176-180
Coauthor Index
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