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ORCIDNishant Sinha 0001
Person information
- affiliation: IBM Research, India
- affiliation (former): NEC Labs, Princeton, NJ, USA
- affiliation (former): Carnegie Mellon University, School of Computer Science, Pittsburgh, PA, USA
Other persons with the same name
- Nishant Sinha — disambiguation page
- Nishant Sinha 0002
![[0000-0002-2090-4889]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-2090-4889")
— Newcastle University, Newcastle upon Tyne, UK (and 1 more) - Nishant Sinha 0003 — Indian Institute of Technology, Roorkee, India
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2010 – 2019
- 2017
[c29]Yu-Fang Chen, Chih-Duo Hong, Ondrej Lengál, Shin-Cheng Mu, Nishant Sinha, Bow-Yaw Wang:
An Executable Sequential Specification for Spark Aggregation. NETYS 2017: 421-438- [i1]Yu-Fang Chen, Chih-Duo Hong, Ondrej Lengál, Shin-Cheng Mu, Nishant Sinha, Bow-Yaw Wang:
An Executable Sequential Specification for Spark Aggregation. CoRR abs/1702.02439 (2017) - 2016
- [c28]Monika Dhok, Murali Krishna Ramanathan, Nishant Sinha:
Type-aware concolic testing of JavaScript programs. ICSE 2016: 168-179 - [c27]Chungha Sung, Markus Kusano, Nishant Sinha, Chao Wang:
Static DOM event dependency analysis for testing web applications. SIGSOFT FSE 2016: 447-459 - [e1]Santonu Sarkar, Ashish Sureka, Domenico Cotroneo, Nishant Sinha, Vibha Singhal Sinha, Radhika Venkatasubramanyam, Padmaja Joshi, R. D. Naik, Pushpendra Singh, JayPrakash Lalchandani:
Proceedings of the 9th India Software Engineering Conference, Goa, India, February 18-20, 2016. ACM 2016, ISBN 978-1-4503-4018-2 [contents] - 2015
- [c26]Nishant Sinha, Rezwana Karim, Monika Gupta:
Simplifying Web Programming. ISEC 2015: 80-89 - [c25]Nishant Sinha, Rezwana Karim:
Responsive designs in a snap. ESEC/SIGSOFT FSE 2015: 544-554 - [c24]Yu-Fang Chen, Chih-Duo Hong, Nishant Sinha, Bow-Yaw Wang:
Commutativity of Reducers. TACAS 2015: 131-146 - 2014
- [c23]Sagar Chaki, Arie Gurfinkel, Nishant Sinha:
Efficient verification of periodic programs using sequential consistency and snapshots. FMCAD 2014: 51-58 - [c22]Vijayaraghavan Murali, Nishant Sinha, Emina Torlak, Satish Chandra:
What Gives? A Hybrid Algorithm for Error Trace Explanation. VSTTE 2014: 270-286 - 2013
- [c21]Suresh Thummalapenta, K. Vasanta Lakshmi, Saurabh Sinha, Nishant Sinha, Satish Chandra:
Guided test generation for web applications. ICSE 2013: 162-171 - [c20]Nishant Sinha, Rezwana Karim:
Compiling mockups to flexible UIs. ESEC/SIGSOFT FSE 2013: 312-322 - 2012
- [c19]Nishant Sinha, Nimit Singhania, Satish Chandra, Manu Sridharan:
Alternate and Learn: Finding Witnesses without Looking All over. CAV 2012: 599-615 - [c18]Jing Yang, Gogul Balakrishnan, Naoto Maeda, Franjo Ivancic, Aarti Gupta, Nishant Sinha, Sriram Sankaranarayanan, Naveen Sharma:
Object Model Construction for Inheritance in C++ and Its Applications to Program Analysis. CC 2012: 144-164 - 2011
- [c17]Nishant Sinha, Chao Wang:
On interference abstractions. POPL 2011: 423-434 - 2010
- [c16]Nishant Sinha:
Modular bug detection with inertial refinement. FMCAD 2010: 199-206 - [c15]Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan, Nishant Sinha, Chao Wang:
Scalable and precise program analysis at NEC. FMCAD 2010: 273-274 - [c14]Nishant Sinha, Chao Wang:
Staged concurrent program analysis. SIGSOFT FSE 2010: 47-56
2000 – 2009
- 2009
- [c13]Vineet Kahlon, Nishant Sinha, Erik Kruus, Yun Zhang:
Static data race detection for concurrent programs with asynchronous calls. ESEC/SIGSOFT FSE 2009: 13-22 - 2008
- [j2]Sagar Chaki, Edmund M. Clarke, Natasha Sharygina, Nishant Sinha:
Verification of evolving software via component substitutability analysis. Formal Methods Syst. Des. 32(3): 235-266 (2008) - [c12]Nishant Sinha:
Symbolic Program Analysis Using Term Rewriting and Generalization. FMCAD 2008: 1-9 - 2007
- [c11]Nishant Sinha, Edmund M. Clarke:
SAT-Based Compositional Verification Using Lazy Learning. CAV 2007: 39-54 - 2006
- [c10]Vineet Kahlon, Aarti Gupta, Nishant Sinha:
Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions. CAV 2006: 286-299 - [c9]Sagar Chaki, Nishant Sinha:
Assume-Guarantee Reasoning for Deadlock. FMCAD 2006: 134-144 - 2005
- [j1]Sagar Chaki, Edmund M. Clarke, Joël Ouaknine, Natasha Sharygina, Nishant Sinha:
Concurrent software verification with states, events, and deadlocks. Formal Aspects Comput. 17(4): 461-483 (2005) - [c8]Sagar Chaki, Edmund M. Clarke, Nishant Sinha, Prasanna Thati:
Automated Assume-Guarantee Reasoning for Simulation Conformance. CAV 2005: 534-547 - [c7]Natasha Sharygina, Sagar Chaki, Edmund M. Clarke, Nishant Sinha:
Dynamic Component Substitutability Analysis. FM 2005: 512-528 - [c6]Edmund M. Clarke, Natasha Sharygina, Nishant Sinha:
Program Compatibility Approaches. FMCO 2005: 243-258 - [c5]Edmund M. Clarke, Himanshu Jain, Nishant Sinha:
Grand Challenge: Model Check Software. VISSAS 2005: 55-68 - 2004
- [c4]Muralidhar Talupur, Nishant Sinha, Ofer Strichman, Amir Pnueli:
Range Allocation for Separation Logic. CAV 2004: 148-161 - [c3]Sagar Chaki, Edmund M. Clarke, Joël Ouaknine, Natasha Sharygina, Nishant Sinha:
State/Event-Based Software Model Checking. IFM 2004: 128-147 - 2003
- [c2]Flavio Lerda, Nishant Sinha, Michael Theobald:
Symbolic Model Checking of Software. SoftMC@CAV 2003: 480-498 - 2002
- [c1]Debasis Samanta, Nishant Sinha, Ajit Pal:
Synthesis of High Performance Low Power Dynamic CMOS Circuits. ASP-DAC/VLSI Design 2002: 99-104
Coauthor Index
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