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Shuu'ichirou Yamamoto
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2020 – today
- 2021
- [j2]Hayato Yoshida
, Yusaku Shiotsu
, Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches. IEEE Open J. Circuits Syst. 2: 520-533 (2021) - 2020
- [j1]Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions. IEICE Electron. Express 17(4): 20200032 (2020)
2010 – 2019
- 2018
- [c7]Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters. NGCAS 2018: 186-189 - 2016
- [c6]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Energy performance of nonvolatile power-gating SRAM using SOTB technology. ESSCIRC 2016: 95-98 - [c5]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Design and implementation of nonvolatile power-gating SRAM using SOTB technology. ISLPED 2016: 338-343 - 2015
- [c4]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology. DATE 2015: 866-871 - 2014
- [c3]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology. APCCAS 2014: 699-702 - 2013
- [c2]Ryosho Nakane
, Yusuke Shuto, Hiroaki Sukegawa
, Zhenchao Wen
, Shuu'ichirou Yamamoto, Seiji Mitani, Masaaki Tanaka, Koichiro Inomata, Satoshi Sugahara:
Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service. ESSDERC 2013: 272-275
2000 – 2009
- 2009
- [c1]Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara:
Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices. CICC 2009: 531-534
Coauthor Index
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