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2010 – 2019
- 2014
[j5]San-Fu Wang, Jan-Ou Wu, Yang-Hsin Fan
, Jhen-Ji Wang:
A Multi-band Low noise amplifier with gain flatness and Bandwidth enhancement. J. Circuits Syst. Comput. 23(2) (2014)- 2012
- [c7]Yang-Hsin Fan, Jan-Ou Wu:
Middleware Software for Embedded Systems. AINA Workshops 2012: 61-65
2000 – 2009
- 2009
- [j4]Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee:
Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion. Circuits Syst. Signal Process. 28(6): 805-817 (2009) - 2008
- [j3]Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee:
GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 365-374 (2008) - [c6]Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee:
Layer assignment considering manufacturability in X-architecture clock tree. CIT 2008: 880-885 - [c5]Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao:
X-clock routing based on pattern matching. SoCC 2008: 357-360 - 2007
- [j2]Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee:
Zero-Skew Driven Buffered RLC Clock Tree Construction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(3): 651-658 (2007) - 2006
- [j1]Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu:
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. J. Inf. Sci. Eng. 22(6): 1585-1599 (2006) - [c4]Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee:
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. APCCAS 2006: 812-815 - [c3]Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao:
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. APCCAS 2006: 1285-1288 - [c2]Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao:
Coupling aware RLC-based clock routings for crosstalk minimization. ISCAS 2006 - 2005
- [c1]Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee:
Zero-Skew Driven for RLC Clock Tree Construction in SoC. ICITA (1) 2005: 561-566
Coauthor Index
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