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Chia-Hsiang Yang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Yu-Chi Lee

> Home > Persons > Chia-Hsiang Yang

Publications

2023
[j36]
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  - journals/jssc/ShenLTY23
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  - https://dblp.org/rec/journals/jssc/ShenLTY23
Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang:
A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator. IEEE J. Solid State Circuits 58(2): 520-529 (2023)
[j35]
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  - journals/jssc/YuLLY23
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  - https://dblp.org/rec/journals/jssc/YuLLY23
Sheng-Jung Yu, Yu-Chi Lee, Liang-Hsin Lin, Chia-Hsiang Yang:
An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices. IEEE J. Solid State Circuits 58(6): 1810-1819 (2023)
2022
[c40]
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  dblp key:
  - conf/vlsit/FuLPY22
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  - https://dblp.org/rec/conf/vlsit/FuLPY22
Zih-Sing Fu, Yu-Chi Lee, Alex Park, Chia-Hsiang Yang:
A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training. VLSI Technology and Circuits 2022: 40-41
2021
[c36]
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  dblp key:
  - conf/asscc/ChenCLZY21
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Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang:
A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring. A-SSCC 2021: 1-3
[c35]
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  - conf/asscc/YuLY21
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Sheng-Jung Yu, Yu-Chi Lee, Chia-Hsiang Yang:
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices. A-SSCC 2021: 1-3
[c33]
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  - conf/isscc/ShenLTY21
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Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang:
4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images. ISSCC 2021: 66-68
2020
[j26]
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  - journals/jssc/LeeCY20
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Yu-Chi Lee, Tai-Shih Chi, Chia-Hsiang Yang:
A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices. IEEE J. Solid State Circuits 55(8): 2247-2258 (2020)
[j25]
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  - journals/tcas/LinLLCCY20
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Yung-Jen Lin, Yu-Chi Lee, Hao-Min Liu, Herming Chiueh, Tai-Shih Chi, Chia-Hsiang Yang:
A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement. IEEE Trans. Circuits Syst. 67-I(12): 4984-4993 (2020)
[c30]
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  - conf/iscas/HsiehLY20
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Yi-Yen Hsieh, Yu-Chi Lee, Chia-Hsiang Yang:
A CycleGAN Accelerator for Unsupervised Learning on Mobile Devices. ISCAS 2020: 1-5
[c25]
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  - conf/vlsic/WenLWKY20
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Chi-Chih Wen, Yu-Chi Lee, Yi-Chung Wu, Chen-Chien Kao, Chia-Hsiang Yang:
A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems. VLSI Circuits 2020: 1-2
2019
[j23]
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  - journals/tbe/QianWYCCCYLLLCL19
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Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem. IEEE Trans. Biomed. Eng. 66(11): 3156-3167 (2019)
[c24]
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  dblp key:
  - conf/aicas/LeeCY19
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Yu-Chi Lee, Tai-Shih Chi, Chia-Hsiang Yang:
A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices. AICAS 2019: 97-101

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