Ting-Kuei Kuan

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ruei-Pin Shen

> Home > Persons > Ting-Kuei Kuan

Publications

2020
[j5]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/KoKSC20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/KoKSC20
Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang:
A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control. IEEE J. Solid State Circuits 55(4): 1043-1050 (2020)
2019
[c5]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsic/KoKSCH019
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/KoKSCH019
Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. VLSI Circuits 2019: 164-
2018
[c4]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsic/KuanWSCHC18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/KuanWSCHC18
Ting-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. VLSI Circuits 2018: 179-180

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.