Tien-Fu Chen

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Tay-Jyi Lin

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Publications

2017
[j32]
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Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3341-3354 (2017)
2016
[j31]
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  - journals/integration/WangTTLWC16
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Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. 54: 24-36 (2016)
[j29]
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  - journals/tcas/WangCYKTCLWC16
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Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 969-973 (2016)
[c50]
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  - conf/socc/ShyuSLYWC16
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Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen:
Variable-length VLIW encoding for code size reduction in embedded processors. SoCC 2016: 296-299
2015
[c49]
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  - conf/asicon/ChouWLLCLW15
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Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON 2015: 1-4
2013
[c40]
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  - conf/isscc/LinCCCWSCLGCCCCSJIWW13
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Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159
[c39]
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  - conf/vlsi/WangCYKTCLWC13
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Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Variation-aware and adaptive-latency accesses for reliable low voltage caches. VLSI-SoC 2013: 358-363
2011
[j22]
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  - journals/mam/ChouCWCL11
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Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin:
Hierarchical circuit-switched NoC for multicore video processing. Microprocess. Microsystems 35(2): 182-199 (2011)
2010
[c35]
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  - conf/date/WenCCL10
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Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin:
RunAssert: A non-intrusive run-time assertion for parallel programs debugging. DATE 2010: 287-290

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