Nalesh S 0001

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with S. Kala

> Home > Persons > Nalesh S 0001

Publications

2023
[j7]
- view
  authority control:
- export record
  dblp key:
  - journals/ijes/MuneebSK23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ijes/MuneebSK23
M. A. Muneeb, Nalesh S, S. Kala:
A physically unclonable function architecture with multiple responses on FPGA. Int. J. Embed. Syst. 16(1): 67-74 (2023)
[c18]
- view
  authority control:
- export record
  dblp key:
  - conf/ises/KalvacherlaGSK23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ises/KalvacherlaGSK23
Abhinav Kalvacherla, Rachana George, Nalesh S, S. Kala:
Approximate CNN on FPGA Using Toom-Cook Multiplier. iSES 2023: 271-276
[c17]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/GSK23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/GSK23
Noble G, Nalesh S, S. Kala:
MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles. VLSID 2023: 264-269
2022
[c16]
- view
  authority control:
- export record
  dblp key:
  - conf/ises/BajjuriSRS22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ises/BajjuriSRS22
Vishnu Bajjuri, Nalesh S, Sree Ranjani Rajendran, S. Kala:
Adiabatic Physical Unclonable Function Using Cross-Coupled Pair. iSES 2022: 278-282
2021
[c14]
- view
  authority control:
- export record
  dblp key:
  - conf/socc/MSS21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/socc/MSS21
Mahesh M, Nalesh S, S. Kala:
Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA. SoCC 2021: 7-12
[c12]
- view
  authority control:
- export record
  dblp key:
  - conf/vdat/MahadurkarSK21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vdat/MahadurkarSK21
Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala:
Hardware Acceleration of SpMV Multiplier for Deep Learning. VDAT 2021: 1-6
2019
[j6]
- view
  authority control:
- export record
  dblp key:
  - journals/iet-cdt/KalaMJS19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/iet-cdt/KalaMJS19
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan:
Radix-4³ based two-dimensional FFT architecture with efficient data reordering scheme. IET Comput. Digit. Tech. 13(2): 78-86 (2019)
[j5]
- view
  authority control:
- export record
  dblp key:
  - journals/tvlsi/KalaJMS19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/KalaJMS19
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan:
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2816-2828 (2019)
[c11]
- view
  authority control:
- export record
  dblp key:
  - conf/socc/KalaJMS19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/socc/KalaJMS19
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan:
Efficient Hardware Acceleration of Convolutional Neural Networks. SoCC 2019: 191-192
[c10]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/KalaMJS19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/KalaMJS19
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan:
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. VLSID 2019: 209-214
2018
[c9]
- view
  authority control:
- export record
  dblp key:
  - conf/dtis/KalaSJMO18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dtis/KalaSJMO18
S. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi:
Two dimensional FFT architecture based on radix-4³ algorithm with efficient output reordering. DTIS 2018: 1-2
[c8]
- view
  authority control:
- export record
  dblp key:
  - conf/ised/KalaPJS18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ised/KalaPJS18
S. Kala, Debdeep Paul, Babita R. Jose, Nalesh Sivanandan:
Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA. ISED 2018: 21-25
2015
[j2]
- view
  authority control:
- export record
  dblp key:
  - journals/jolpe/KalaNNN15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jolpe/KalaNNN15
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. 11(3): 426-435 (2015)
2014
[c3]
- view
  authority control:
- export record
  dblp key:
  - conf/ised/KalaSNN14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ised/KalaSNN14
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED 2014: 20-24
2013
[c1]
- view
  authority control:
- export record
  dblp key:
  - conf/iscas/KalaNMNN13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/KalaNMNN13
S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan:
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS 2013: 3034-3037

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.