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ORCIDWei Hwang
Publications
- 2022
[c84]Wei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang:
Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. ISOCC 2022: 169-170- 2021
- [j29]Wei Lu
, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang:
An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 776-788 (2021) - [j28]Po-Tsang Huang, I-Chen Wu, Chin-Yang Lo, Wei Hwang:
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks. IEEE Open J. Circuits Syst. 2: 131-143 (2021) - [c83]Po-Tsang Huang, Ting-Wei Liu, Wei Lu, Yu-Hsien Lin, Wei Hwang:
An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks. ISOCC 2021: 260-261 - 2020
- [c82]Chin-Yang Lo, Po-Tsang Huang, Wei Hwang:
Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. AICAS 2020: 320-323 - [c81]Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen:
Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. SoCC 2020: 242-247 - 2019
- [c80]I-Chen Wu, Po-Tsang Huang, Chin-Yang Lo, Wei Hwang:
An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network. AICAS 2019: 42-45 - [c79]Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. SoCC 2019: 248-253 - 2018
- [c78]Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. SoCC 2018: 272-277 - [c77]Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. VLSI-DAT 2018: 1-4 - 2017
- [j27]Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. IEEE Trans. Biomed. Circuits Syst. 11(5): 1013-1025 (2017) - [j26]Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang:
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1791-1802 (2017) - [c76]Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS 2017: 1-4 - 2016
- [c74]Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. ISCAS 2016: 1302-1305 - [c73]Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang:
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. SoCC 2016: 18-23 - 2015
- [c70]Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang:
Energy-efficient gas recognition system with event-driven power control. SoCC 2015: 245-250 - [c69]Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT 2015: 1-4 - [c68]Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang:
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. VLSI-DAT 2015: 1-4 - 2014
- [j24]Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong:
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. IEEE Trans. Biomed. Circuits Syst. 8(6): 810-823 (2014) - [c67]Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang:
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. A-SSCC 2014: 129-132 - [c64]Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Energy-efficient configurable discrete wavelet transform for neural sensing applications. ISCAS 2014: 1841-1844 - [c63]Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, Ho-Ming Tong:
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. ISSCC 2014: 320-321 - [c62]Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang:
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. SoCC 2014: 76-81 - [c60]Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. VLSI-DAT 2014: 1-4 - 2013
- [c58]Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. BioCAS 2013: 238-241 - [c55]Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong:
Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC 2013: 102-103 - 2012
- [j20]Po-Tsang Huang, Wei Hwang:
Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electr. Comput. Eng. 2012: 697039:1-697039:19 (2012) - [c51]Po-Jen Yang, Po-Tsang Huang, Wei Hwang:
Substrate noise suppression technique for power integrity of TSV 3D integration. ISCAS 2012: 3274-3277 - [c47]Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang:
On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC 2012: 370-375 - [c46]Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang:
A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. VLSI-DAT 2012: 1-4 - 2011
- [j14]Po-Tsang Huang, Wei Hwang:
Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(11): 2412-2424 (2011) - [j13]Po-Tsang Huang, Wei Hwang:
A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. IEEE J. Solid State Circuits 46(2): 507-519 (2011) - [c40]Po-Tsang Huang, Yung Chang, Wei Hwang:
On-demand memory sub-system for multi-core SoCs. SoCC 2011: 122-127 - 2010
- [j8]Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang:
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. 6(4): 551-562 (2010) - [c35]Tien-Hung Lin, Po-Tsang Huang, Wei Hwang:
Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC 2010: 209-212 - 2009
- [c32]Po-Tsang Huang, Wei Hwang:
An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. SoCC 2009: 375-378 - 2008
- [c30]Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang:
"Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS 2008: 3322-3325 - [c29]Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang:
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS 2008: 3342-3345 - [c28]Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang:
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS 2008: 77-83 - [c26]Mu-Tien Chang, Po-Tsang Huang, Wei Hwang:
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178 - 2007
- [c21]Mu-Tien Chang, Po-Tsang Huang, Wei Hwang:
A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC 2007: 207-210 - 2006
- [c19]Jen-Wei Yang, Po-Tsang Huang, Wei Hwang:
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS 2006: 666-669 - [c18]Po-Tsang Huang, Wei-Keng Chang, Wei Hwang:
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS 2006: 1301-1304 - [c14]Po-Tsang Huang, Wei Hwang:
2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS 2006
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last updated on 2024-04-21 17:52 CEST by the dblp team
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