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ORCIDTakafumi Fukushima
- > Home > Persons > Takafumi Fukushima
Publications
- 2021
[c62]Takafumi Fukushima, Shinichi Sakuyama, Masatomo Takahashi, Hiroyuki Hashimoto, Jichoel Bea, Theodorus Marcello, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi, Mariappan Murugesan:
Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing. 3DIC 2021: 1-4- 2019
- [c50]Mariappan Murugesan, Mitsumasa Koyanagi, Hiroyuki Hashimoto, Ji Chel Bea, Takafumi Fukushima:
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration. 3DIC 2019: 1-4 - 2018
- [c47]Mariappan Murugesan, Takafumi Fukushima
, Ji Chel Bea, Hiroyuki Hashimoto, Mitsu Koyanagi:
Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal. IRPS 2018: 4 - 2016
- [j3]Takafumi Fukushima, Hideto Hashiguchi, Hiroshi Yonekura, Hisashi Kino, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration. Micromachines 7(10): 184 (2016) - [c44]Takafumi Fukushima, Mariappan Murugesan, Shin Ohsaki, Hiroyuki Hashimoto, Jichoel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
New concept of TSV formation methodology using Directed Self-Assembly (DSA). 3DIC 2016: 1-4 - [c42]Kang Wook Lee, Ai Nakamura, Jicheol Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tanaka Tanaka, Mitsumasa Koyanagi:
Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications. 3DIC 2016: 1-5 - [c41]Mariappan Murugesan, Jichel Bea, Takafumi Fukushima, Makoto Motoyoshi, Tetsu Tanaka, Mitsumasa Koyanagi:
Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology. 3DIC 2016: 1-4 - 2015
- [c40]K. W. Lee, Ji Chel Bea, Mitsu Koyanagi, Takafumi Fukushima, Tetsu Tanaka:
Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University. 3DIC 2015: FS2.1-FS2.5 - [c39]K. W. Lee, Chisato Nagai, Ai Nakamura, Hiroki Aizawa, Ji Chel Bea, Mitsumasa Koyanagi, Hideto Hashiguchi, Takafumi Fukushima, Tanaka Tanaka:
Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers. 3DIC 2015: TS1.2.1-TS1.2.4 - [c36]Takafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi:
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. 3DIC 2015: TS7.4.1-TS7.4.4 - [c35]Mariappan Murugesan, Jichoel Bea, Hiroyuki Hashimoto, K. W. Lee, Mitsu Koyanagi, Takafumi Fukushima, Tetsu Tanaka:
Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study. 3DIC 2015: TS8.10.1-TS8.10.5 - [c33]Kang Wook Lee, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. IRPS 2015: 4 - 2014
- [c32]Takafumi Fukushima, Yuka Ito, Mariappan Murugesan, Jicheol Bea, Kang Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi:
Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. 3DIC 2014: 1-4 - [c31]K. W. Lee, Chisato Nagai, Ai Nakamura, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tanaka Tanaka, Mitsumasa Koyanagi:
Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV. 3DIC 2014: 1-4 - [c30]Mariappan Murugesan, Takafumi Fukushima, Ji Chel Bea, K. W. Lee, Mitsu Koyanagi, Y. Imai, S. Kimura, Tetsu Tanaka:
Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI. 3DIC 2014: 1-4 - 2013
- [c28]Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Mitsumasa Koyanagi:
Development of via-last 3D integration technologies using a new temporary adhesive system. 3DIC 2013: 1-4 - [c27]Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Ho-Young Son, M.-S. Suh, K.-Y. Byun, N.-S. Kim, Kang Wook Lee, Mitsumasa Koyanagi:
3D memory chip stacking by multi-layer self-assembly technology. 3DIC 2013: 1-4 - [c24]Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. 3DIC 2013: 1-4 - [c23]Mariappan Murugesan, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi, Yuji Sutou, H. Wang, J. Koike:
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. 3DIC 2013: 1-4 - 2011
- [j2]Takafumi Fukushima, Takayuki Konno, Eiji Iwata, Risato Kobayashi, Toshiya Kojima, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. Micromachines 2(1): 49-68 (2011) - [c22]Takafumi Fukushima, Yuki Ohara, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Temporary bonding strength control for self-assembly-based 3D integration. 3DIC 2011: 1-4 - [c18]Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Yuki Ohara, Tetsu Tanaka, Mitsumasa Koyanagi:
High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs. 3DIC 2011: 1-4 - [c14]Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI. 3DIC 2011: 1-4 - 2010
- [c12]Takafumi Fukushima, Eiji Iwata, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. 3DIC 2010: 1-5 - [c10]Mariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. 3DIC 2010: 1-5 - [c9]Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI. 3DIC 2010: 1-4 - 2009
- [c7]Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki, Hisashi Kino, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. 3DIC 2009: 1-5 - [c4]Kang Wook Lee, Shigeyuki Kanno, Yuki Ohara, Kouji Kiyoyama, Ji Chel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Heterogeneous integration technology for MEMS-LSI multi-chip module. 3DIC 2009: 1-6 - [c3]Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang Wook Lee, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. 3DIC 2009: 1-6
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