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Saeed Safari
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Publications
- 2012
- [c34]M. H. Haghbayan, Saeed Safari, Zainalabedin Navabi:
Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. DDECS 2012: 42-45 - [c33]Mohammadreza Najafi, Saeed Safari, Zainalabedin Navabi:
Soft Error Analysis on Communication Channels in On-Chip Communication Networks. DSD 2012: 852-857 - [c32]Reza Nakhjavani, Ali Shahabi, Saeed Safari, Zainalabedin Navabi:
A novel graceful degradable routing algorithm for 3D on-chip networks. INA-OCMC@HiPEAC 2012: 17-20 - 2010
- [c25]Amirali Ghofrani, Fatemeh Javaheri, Saeed Safari, Zainalabedin Navabi:
Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization. SoC 2010: 111-114 - 2008
- [c17]Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi:
A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. IOLTS 2008: 173-174 - [c16]Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi:
Reliability in Application Specific Mesh-Based NoC Architectures. IOLTS 2008: 207-212 - 2007
- [c11]Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi:
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS 2007: 247-250 - [c9]Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi:
On-Chip Verification of NoCs Using Assertion Processors. DSD 2007: 535-538
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last updated on 2024-04-25 01:34 CEST by the dblp team
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