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Hayden Kwok-Hay So
- > Home > Persons > Hayden Kwok-Hay So
Publications
- 2016
- [j10]Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang:
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. SIGARCH Comput. Archit. News 44(4): 92-97 (2016) - 2013
- [j8]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
Design space exploration for sparse matrix-matrix multiplication on FPGAs. Int. J. Circuit Theory Appl. 41(2): 205-219 (2013) - [c17]Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So:
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. FCCM 2013: 228 - 2012
- [j7]Colin Yu Lin, Hayden Kwok-Hay So:
Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis. SIGARCH Comput. Archit. News 40(5): 58-63 (2012) - [c15]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). FPGA 2012: 270 - 2011
- [c12]Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong:
A Model for Peak Matrix Performance on FPGAs. FCCM 2011: 251 - [c11]Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong:
A Model for Matrix Multiplication Performance on FPGAs. FPL 2011: 305-310 - 2010
- [c10]Colin Yu Lin, Zheng Zhang, Ngai Wong, Hayden Kwok-Hay So:
Design space exploration for sparse matrix-matrix multiplication on FPGAs. FPT 2010: 369-372 - 2009
- [c9]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
Operation scheduling for FPGA-based reconfigurable computers. FPL 2009: 481-484
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