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ORCIDSai-Weng Sin
- > Home > Persons > Sai-Weng Sin
Publications
- 2023
[j58]Shulin Zhao
, Mingqiang Guo, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins, Sai-Weng Sin:
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward. IEEE J. Solid State Circuits 58(10): 2722-2732 (2023)- [j56]Yue Hu, Yuekai Liu, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi:
A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4729-4741 (2023) - [j55]Mingqiang Guo, Liang Qi, Weibing Zhao, Gang Xiao, Rui Paulo Martins, Sai-Weng Sin:
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4767-4780 (2023) - [j54]Gaofeng Tan, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi:
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4781-4792 (2023) - [j53]Jingying Zhang, Sai-Weng Sin, Yan Liu, Fan Ye, Guoxing Wang, Maurits Ortmanns, Liang Qi:
On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 356-360 (2023) - [j52]Kaiquan Chen, Biao Wang, Yan Liu, Fan Ye, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi:
A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2724-2728 (2023) - [c67]Ruiqi Gao, Mingqiang Guo, Sai-Weng Sin, Liang Qi, Biao Wang, Guoxing Wang, Rui Paulo Martins:
Weightings in Incremental ADCs: A Tutorial Review. CICC 2023: 1-8 - 2022
- [j50]Mingqiang Guo, Sai-Weng Sin, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins:
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2564-2569 (2022) - [j49]Liang Qi, Yuekai Liu, Sai-Weng Sin, Xinpeng Xing, Guoxing Wang, Maurits Ortmanns, Rui Paulo Martins:
Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2623-2628 (2022) - [c65]Mingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao, Rui Paulo Martins:
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. CICC 2022: 1-2 - [c64]Ke Li, Sai-Weng Sin, Liang Qi, Weibing Zhao, Guoxing Wang, Rui Paulo Martins:
A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. ISCAS 2022: 551-555 - 2021
- [j46]Dongyang Jiang, Liang Qi, Sai-Weng Sin, Franco Maloberti, Rui Paulo Martins:
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation. IEEE J. Solid State Circuits 56(8): 2375-2387 (2021) - [c63]Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang:
Advances in Continuous-time MASH ΔΣ Modulators. ASICON 2021: 1-4 - [c61]Xinyu Qin, Jingying Zhang, Liang Qi, Sai-Weng Sin, Rui Paulo Martins, Guoxing Wang:
Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. ISCAS 2021: 1-5 - 2020
- [j43]Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns:
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. IEEE J. Solid State Circuits 55(2): 344-355 (2020) - [c59]Dongyang Jiang, Liang Qi, Sai-Weng Sin, Franco Maloberti, Rui Paulo Martins:
A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS. VLSI Circuits 2020: 1-2 - 2019
- [c58]Liang Qi, Sai-Weng Sin, Rui Paulo Martins:
Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. ASICON 2019: 1-4 - [c54]Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns:
A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. ISSCC 2019: 336-338 - 2017
- [j22]Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2641-2654 (2017)
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