Amrith Sukumaran

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▷ joint publications with Shanthi Pavan

> Home > Persons > Amrith Sukumaran

Publications

2017
[j5]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/BillaSP17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/BillaSP17
Sujith Billa, Amrith Sukumaran, Shanthi Pavan:
Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping. IEEE J. Solid State Circuits 52(9): 2350-2361 (2017)
2016
[j4]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/SukumaranP16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/SukumaranP16
Amrith Sukumaran, Shanthi Pavan:
Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs. IEEE J. Solid State Circuits 51(7): 1619-1629 (2016)
[c2]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/BillaSP16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/BillaSP16
Sujith Billa, Amrith Sukumaran, Shanthi Pavan:
15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts. ISSCC 2016: 276-277
2015
[c1]
- view
  authority control:
- export record
  dblp key:
  - conf/esscirc/SukumaranP15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/esscirc/SukumaranP15
Amrith Sukumaran, Shanthi Pavan:
A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC. ESSCIRC 2015: 217-220
2014
[j3]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/SukumaranP14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/SukumaranP14
Amrith Sukumaran, Shanthi Pavan:
Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback. IEEE J. Solid State Circuits 49(11): 2515-2525 (2014)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.