Frank O'Mahony

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ajay Balankutty

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Publications

2023
[j12]
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Ahmad Khairi, Yoel Krupnik, Amir Laufer, Yoav Segal, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Sabag, Vitali Rahinski, Idan Lotan, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky Grafi, Udi Virobnik, Dror Lazar, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo, Peng Mike Li, Frank O'Mahony, Ariel Cohen:
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. IEEE J. Solid State Circuits 58(1): 8-18 (2023)
2022
[j11]
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Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen T. Kim, Yutao Liu, Savyasaachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yoav Segal, Yongping Fan, Peng Li, Frank O'Mahony:
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. IEEE J. Solid State Circuits 57(1): 6-20 (2022)
2021
[c31]
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Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen Kim, Yutao Liu, Savyassachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yongping Fan, Frank O'Mahony:
8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. ISSCC 2021: 126-128
[c30]
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Shiva Kiran, Ajay Balankutty, Yutao Liu, Rajeev Dokania, Hariprasath Venkataraman, Priya Wali, Stephen Kim, Yoel Krupnik, Ariel Cohen, Frank O'Mahony:
A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS. VLSI Circuits 2021: 1-2
2020
[c29]
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Wilfred Gomes, Sanjeev Khushu, Doug B. Ingerly, Patrick N. Stover, Nasirul I. Chowdhury, Frank O'Mahony, Ajay Balankutty, Noam Dolev, Martin G. Dixon, Lei Jiang, Surya Prekke, Biswajit Patra, Pavel V. Rott, Rajesh Kumar:
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm², 1mm Package-on-Package. ISSCC 2020: 144-146
2019
[j10]
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Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Dan Shi, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. IEEE J. Solid State Circuits 54(1): 29-42 (2019)
2018
[c27]
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Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. ISSCC 2018: 102-104
2015
[c18]
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Jihwan Kim, Ajay Balankutty, Amr Elshazly, Yan-Yu Huang, Hang Song, Kai Yu, Frank O'Mahony:
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. ISSCC 2015: 1-3
2014
[c15]
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Amr Elshazly, Ajay Balankutty, Yan-Yu Huang, Kai Yu, Frank O'Mahony:
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. VLSIC 2014: 1-2

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