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Yih-Lang Li
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Publications
- 2014
- [j13]Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li:
Minimizing Critical Area on Gridless Wire Ordering, Sizing and Spacing. J. Inf. Sci. Eng. 30(1): 157-177 (2014) - [i1]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: a triple patterning lithography aware detailed router. CoRR abs/1402.2906 (2014) - 2012
- [c22]Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li:
Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. ASP-DAC 2012: 437-442 - [c21]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: A triple patterning lithography aware detailed router. ICCAD 2012: 123-129 - 2011
- [j9]Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li:
Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1335-1348 (2011) - [c15]Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li:
Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. ICCAD 2011: 283-289 - [c14]Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li:
Gridless wire ordering, sizing and spacing with critical area minimization. ISQED 2011: 646-653 - 2010
- [c12]Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li:
Dead via minimization by simultaneous routing and redundant via insertion. ASP-DAC 2010: 657-662 - [c10]Yen-Hung Lin, Yih-Lang Li:
Double patterning lithography aware gridless detailed routing with innovative conflict graph. DAC 2010: 398-403 - 2009
- [c7]De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, Yih-Lang Li:
Topology-driven cell layout migration with collinear constraints. ICCD 2009: 439-444 - [c6]Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li:
Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization. ISPD 2009: 151-158
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