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Daisuke Yashima

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▷ joint publications with Kentaro Yoshioka

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Publications

2018
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  dblp key:
  - conf/isscc/KawaiAISAMTKUHS18
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/KawaiAISAMTKUHS18
Shusuke Kawai, Hiromitsu Aoyama, Rui Ito, Yutaka Shimizu, Mitsuyuki Ashida, Asuka Maki, Tomohiko Takeuchi, Hiroyuki Kobayashi, Go Urakawa, Hiroaki Hoshino, Shigehito Saigusa, Kazushi Koyama, Makoto Morita, Ryuichi Nihei, Daisuke Goto, Motoki Nagata, Kengo Nakata, Katsuyuki Ikeuchi, Kentaro Yoshioka, Ryoichi Tachibana, Makoto Arai, Chen Kong Teh, Atsushi Suzuki, Hiroshi Yoshida, Yosuke Hagiwara, Takayuki Kato, Ichiro Seto, Tomoya Horiguchi, Koichiro Ban, Kyosuke Takahashi, Hirotsugu Kajihara, Toshiyuki Yamagishi, Yuki Fujimura, Kazuhisa Horiuchi, Katsuya Nonin, Kengo Kurose, Hideki Yamada, Kentaro Taniguchi, Masahiro Sekiya, Takeshi Tomizawa, Daisuke Taki, Masaaki Ikuta, Tomoya Suzuki, Yuki Ando, Daisuke Yashima, Takahisa Kaihotsu, Hiroki Mori, Kensuke Nakanishi, Takeshi Kumagaya, Yasuo Unekawa, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo:
An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. ISSCC 2018: 442-444
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  - conf/vlsic/YoshiokaTBYMSO18
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Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka:
PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. VLSI Circuits 2018: 263-264
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  - journals/corr/abs-1808-09335
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Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka:
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators. CoRR abs/1808.09335 (2018)

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