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Publications
- 2021
[j45]Miguel Morales-Sandoval
, Luis Armando Rodriguez Flores, René Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, Ignacio Algredo-Badillo:
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. J. Sensors 2021: 8860413:1-8860413:13 (2021)- 2018
- [i2]Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido:
An FPGA-based programmable processor for bilinear pairings. IACR Cryptol. ePrint Arch. 2018: 1014 (2018) - 2017
- [c45]Luis Armando Rodriguez Flores, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo:
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. LASCAS 2017: 1-4 - 2014
- [j30]Rommel García, Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido:
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Comput. Electr. Eng. 40(1): 194-202 (2014) - 2013
- [j24]Miguel Morales-Sandoval, Claudia Feregrino Uribe, Paraskevas Kitsos, René Cumplido:
Area/performance trade-off analysis of an FPGA digit-serial GF(2m)GF(2m) Montgomery multiplier based on LFSR. Comput. Electr. Eng. 39(2): 542-549 (2013) - [j20]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsystems 37(6-7): 750-757 (2013) - [c30]Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo:
A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. ReCoSoC 2013: 1-8 - 2012
- [c28]Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido:
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI 2012: 63-68 - 2011
- [c27]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD 2011: 543-549 - 2010
- [j13]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Comput. Electr. Eng. 36(3): 565-577 (2010) - [j9]Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo:
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. J. Circuits Syst. Comput. 19(2): 425-433 (2010) - 2009
- [j8]Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo:
An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. Comput. Electr. Eng. 35(1): 54-58 (2009) - [c19]Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo:
A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. ENC 2009: 345-350 - 2008
- [j3]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Trans. Inf. Syst. 91-D(10): 2519-2523 (2008) - [c12]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig 2008: 421-426
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