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Jun Yang 0006

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Wei Ge

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Publications

2023
[j76]
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  - journals/dt/LiuCZDZGWGY23
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  persistent URL:
  - https://dblp.org/rec/journals/dt/LiuCZDZGWGY23
Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Renyuan Zhang, Yu Gong, Zhen Wang, Wei Ge, Jun Yang:
Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition. IEEE Des. Test 40(3): 26-35 (2023)
2020
[j48]
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  - journals/tcas/0019C0SSZ0GG0S20
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  - https://dblp.org/rec/journals/tcas/0019C0SSZ0GG0S20
Bo Liu, Hao Cai, Zhen Wang, Yuhao Sun, Zeyu Shen, Wentao Zhu, Yan Li, Yu Gong, Wei Ge, Jun Yang, Longxing Shi:
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor. IEEE Trans. Circuits Syst. 67-I(12): 4733-4746 (2020)
2018
[j34]
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  - journals/ieiceee/WangXLRGYGY18
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  - https://dblp.org/rec/journals/ieiceee/WangXLRGYGY18
Zhen Wang, Mengwen Xia, Bo Liu, Xing Ruan, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang:
EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier. IEICE Electron. Express 15(8): 20180212 (2018)
[c15]
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  dblp key:
  - conf/icdsp/LiuGQGYGY18
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  - https://dblp.org/rec/conf/icdsp/LiuGQGYGY18
Bo Liu, Shisheng Guo, Hai Qin, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang:
An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing. DSP 2018: 1-5
[c12]
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  dblp key:
  - conf/trustcom/ChenGYLY18
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  - https://dblp.org/rec/conf/trustcom/ChenGYLY18
Shenghua Chen, Wei Ge, Jinjiang Yang, Bo Liu, Jun Yang:
A Power Analysis Attack Countermeasure Based on Random Execution. TrustCom/BigDataSE 2018: 1474-1479
2017
[j24]
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  - journals/ieiceee/GuoZWNLGY17
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Jingjing Guo, Jizhe Zhu, Min Wang, Jianxin Nie, Xinning Liu, Wei Ge, Jun Yang:
Analytical inverter chain's delay and its variation model for sub-threshold circuits. IEICE Electron. Express 14(11): 20170390 (2017)
[c8]
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  dblp key:
  - conf/sips/GongXLGY0S17
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Yu Gong, Tingting Xu, Bo Liu, Wei Ge, Jinjiang Yang, Jun Yang, Longxing Shi:
Processing LSTM in memory using hybrid network expansion model. SiPS 2017: 1-6
[c7]
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  dblp key:
  - conf/ssci/LiuRXGYGY17
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Bo Liu, Xing Ruan, Mengwen Xia, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang:
An energy-efficient accelerator for hybrid bit-width DNNs. SSCI 2017: 1-8

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