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Jeffrey T. Draper

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ji Li 0006

> Home > Persons > Jeffrey T. Draper

Publications

2019
[j13]
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  - journals/iet-cdt/ZhangLCZDB19
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  - https://dblp.org/rec/journals/iet-cdt/ZhangLCZDB19
Yang Zhang, Ji Li, Huimei Cheng, Haipeng Zha, Jeffrey Draper, Peter A. Beerel:
Yield modelling and analysis of bundled data and ring-oscillator based designs. IET Comput. Digit. Tech. 13(3): 262-272 (2019)
[j12]
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  - journals/integration/LiYLRDDNQYW19
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  - https://dblp.org/rec/journals/integration/LiYLRDDNQYW19
Ji Li, Zihao Yuan, Zhe Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Shahin Nazarian, Qinru Qiu, Bo Yuan, Yanzhi Wang:
Normalization and dropout for stochastic computing-based deep convolutional neural networks. Integr. 65: 395-403 (2019)
[j11]
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  dblp key:
  - journals/tcad/LiLRCDQDYTQW19
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  - https://dblp.org/rec/journals/tcad/LiLRCDQDYTQW19
Zhe Li, Ji Li, Ao Ren, Ruizhe Cai, Caiwen Ding, Xuehai Qian, Jeffrey Draper, Bo Yuan, Jian Tang, Qinru Qiu, Yanzhi Wang:
HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1543-1556 (2019)
2018
[c80]
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  - conf/isqed/MehtaHCBMLDN18
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  - https://dblp.org/rec/conf/isqed/MehtaHCBMLDN18
Raghav Mehta, Yuyang Huang, Mingxi Cheng, Shrey Bagga, Nishant Mathur, Ji Li, Jeffrey Draper, Shahin Nazarian:
High performance training of deep neural networks using pipelined hardware acceleration and distributed memory. ISQED 2018: 383-388
[c79]
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  - conf/isvlsi/0001LRDDQ0W18
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  - https://dblp.org/rec/conf/isvlsi/0001LRDDQ0W18
Zhe Li, Ji Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Qinru Qiu, Bo Yuan, Yanzhi Wang:
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks Using Stochastic Computing. ISVLSI 2018: 28-33
[i2]
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  - journals/corr/abs-1805-04142
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Zhe Li, Ji Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Qinru Qiu, Bo Yuan, Yanzhi Wang:
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks using Stochastic Computing. CoRR abs/1805.04142 (2018)
2017
[j10]
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  - journals/todaes/LiD17
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Ji Li, Jeffrey Draper:
Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits. ACM Trans. Design Autom. Electr. Syst. 22(3): 57:1-57:21 (2017)
[c78]
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  - conf/date/LiRLQYDW17
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Zhe Li, Ao Ren, Ji Li, Qinru Qiu, Bo Yuan, Jeffrey Draper, Yanzhi Wang:
Structural design optimization for deep convolutional neural networks using stochastic computing. DATE 2017: 250-253
[c77]
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  dblp key:
  - conf/glvlsi/ChengLDNW17
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Huimei Cheng, Ji Li, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang:
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems. ACM Great Lakes Symposium on VLSI 2017: 427-430
[c76]
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  - conf/glvlsi/YuanLLDRYQDW17
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Zihao Yuan, Ji Li, Zhe Li, Caiwen Ding, Ao Ren, Bo Yuan, Qinru Qiu, Jeffrey Draper, Yanzhi Wang:
Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural Networks. ACM Great Lakes Symposium on VLSI 2017: 467-470
[c75]
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  - conf/ijcnn/LiY0DRQDW17
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Ji Li, Zihao Yuan, Zhe Li, Caiwen Ding, Ao Ren, Qinru Qiu, Jeffrey Draper, Yanzhi Wang:
Hardware-driven nonlinear activation for stochastic computing based deep convolutional neural networks. IJCNN 2017: 1230-1236
[i1]
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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/LiYLDRQDW17
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Ji Li, Zihao Yuan, Zhe Li, Caiwen Ding, Ao Ren, Qinru Qiu, Jeffrey T. Draper, Yanzhi Wang:
Hardware-Driven Nonlinear Activation for Stochastic Computing Based Deep Convolutional Neural Networks. CoRR abs/1703.04135 (2017)
2016
[c74]
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  - conf/dac/LiD16
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Ji Li, Jeffrey Draper:
Accelerating soft-error-rate (SER) estimation in the presence of single event transients. DAC 2016: 55:1-55:6
[c72]
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  - conf/isvlsi/LiD16
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Ji Li, Jeffrey T. Draper:
Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements. ISVLSI 2016: 737-742

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