Prashant Saxena

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with C. L. Liu 0001

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Publications

2003
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Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang:
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 879-887 (2003)
2001
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Prashant Saxena, C. L. Liu:
Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 503-515 (2001)
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Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737
2000
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Prashant Saxena, C. L. Liu:
A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6): 691-702 (2000)
1999
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Prashant Saxena, C. L. Liu:
Crosstalk Minimization Using Wire Perturbations. DAC 1999: 100-103
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Prashant Saxena, Peichen Pan, C. L. Liu:
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407
1998
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Prashant Saxena, C. L. Liu:
A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD 1998: 124-127
1996
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  - conf/europar/BoppanaSBFL96
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Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu:
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831

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