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Rizwan Bashirullah
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Publications
- 2006
- [j4]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards:
A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling. IEEE J. Solid State Circuits 41(2): 461-473 (2006) - 2005
- [j3]Gurhan Alper Kendir, Wentai Liu, Guoxing Wang, Mohanasankar Sivaprakasam, Rizwan Bashirullah, Mark S. Humayun, James D. Weiland:
An optimal design methodology for inductive power link with class-E amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(5): 857-866 (2005) - 2004
- [j2]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards:
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 876-880 (2004) - [c7]Liang Zhang, Wentai Liu, Rizwan Bashirullah, John M. Wilson, Paul D. Franzon:
Simplified delay design guidelines for on-chip global interconnects. ACM Great Lakes Symposium on VLSI 2004: 29-32 - [c6]Guoxing Wang, Wentai Liu, Rizwan Bashirullah, Mohanasankar Sivaprakasam, Gurhan Alper Kendir, Ying Ji, Mark S. Humayun, James D. Weiland:
A closed loop transcutaneous power transfer system for implantable devices with enhanced stability. ISCAS (4) 2004: 17-20 - [c5]Gurhan Alper Kendir, Wentai Liu, Rizwan Bashirullah, Guoxing Wang, Mark S. Humayun, James D. Weiland:
An efficient inductive power link design for retinal prosthesis. ISCAS (4) 2004: 41-44 - 2003
- [j1]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Current-mode signaling in deep submicrometer global interconnects. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 406-417 (2003) - [c4]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Low-power design methodology for an on-chip bus with adaptive bandwidth capability. DAC 2003: 628-633 - [c3]Rizwan Bashirullah, Wentai Liu, Ying Ji, Gurhan Alper Kendir, Mohanasankar Sivaprakasam, Guoxing Wang, B. Pundi:
A smart bi-directional telemetry unit for retinal prosthetic device. ISCAS (5) 2003: 5-8 - [c2]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Accurate delay model and experimental verification for current/voltage mode on-chip interconnects. ISCAS (5) 2003: 169-172 - 2002
- [c1]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Delay and power model for current-mode signaling in deep submicron global interconnects. CICC 2002: 513-516
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