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ORCIDDan Alexandrescu
- > Home > Persons > Dan Alexandrescu
Publications
- 2021
[c42]Aneesh Balakrishnan
, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux:
Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis. ISQED 2021: 24-30- [c41]Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin:
On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. VLSI-SoC 2021: 1-6 - [i10]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. CoRR abs/2104.01812 (2021) - [i9]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. CoRR abs/2104.01900 (2021) - [i8]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. CoRR abs/2104.01908 (2021) - [i7]Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux:
Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models. CoRR abs/2104.10941 (2021) - 2020
- [c39]Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux:
Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models. IOLTS 2020: 1-6 - [c38]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. IOLTS 2020: 1-7 - [c37]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. MECO 2020: 1-5 - [i6]Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. CoRR abs/2002.05455 (2020) - [i5]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. CoRR abs/2002.08882 (2020) - [i4]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. CoRR abs/2002.09945 (2020) - [i3]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. CoRR abs/2008.13664 (2020) - 2019
- [j6]Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu:
Understanding multidimensional verification: Where functional meets non-functional. Microprocess. Microsystems 71 (2019) - [c36]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. AHS 2019: 72-78 - [c34]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. DSN (Supplements) 2019: 35-41 - [c33]Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. DTIS 2019: 1-6 - [c32]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. IOLTS 2019: 7-14 - [c31]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. NORCAS 2019: 1-7 - 2018
- [c30]Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs:
A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs. AHS 2018: 120-126
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