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Hiroyuki Hashimoto
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Publications
- 2021
- [c19]Takafumi Fukushima, Shinichi Sakuyama, Masatomo Takahashi, Hiroyuki Hashimoto, Jichoel Bea, Theodorus Marcello, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi, Mariappan Murugesan:
Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing. 3DIC 2021: 1-4 - [c18]Koji Kiyoyama, Yoshihiko Horio, Takafumi Fukushima, Hiroyuki Hashimoto, Takemori Orima, Mitsumasa Koyanagi:
Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing. 3DIC 2021: 1-4 - 2019
- [c16]Koji Kiyoyama, Qian Zhengy, Hiroyuki Hashimoto, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka:
Development of a CDS Circuit for 3-D Stacked Neural Network Chip using CMOS Analog Signal Processing. 3DIC 2019: 1-4 - [c15]Mariappan Murugesan, Mitsumasa Koyanagi, Hiroyuki Hashimoto, Ji Chel Bea, Takafumi Fukushima:
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration. 3DIC 2019: 1-4 - 2018
- [c13]Mariappan Murugesan, Takafumi Fukushima, Ji Chel Bea, Hiroyuki Hashimoto, Mitsu Koyanagi:
Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal. IRPS 2018: 4 - 2016
- [c11]Takafumi Fukushima, Mariappan Murugesan, Shin Ohsaki, Hiroyuki Hashimoto, Jichoel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
New concept of TSV formation methodology using Directed Self-Assembly (DSA). 3DIC 2016: 1-4 - 2015
- [c9]Takafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi:
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. 3DIC 2015: TS7.4.1-TS7.4.4 - [c8]Mariappan Murugesan, Jichoel Bea, Hiroyuki Hashimoto, K. W. Lee, Mitsu Koyanagi, Takafumi Fukushima, Tetsu Tanaka:
Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study. 3DIC 2015: TS8.10.1-TS8.10.5 - 2013
- [c6]Hiroyuki Hashimoto, Takafumi Fukushima, Kang Wook Lee, Mitsumasa Koyanagi, Tetsu Tanaka:
Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. 3DIC 2013: 1-5 - [c5]Kouji Kiyoyama, Y. Sato, Hiroyuki Hashimoto, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor. 3DIC 2013: 1-4
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