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Shekhar Borkar
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Publications
- 2003
- [j11]Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar:
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits 38(5): 755-761 (2003) - [c22]Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson:
Bitline leakage equalization for sub-100nm caches. ESSCIRC 2003: 401-404 - [c21]Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy, Shekhar Borkar:
Low voltage sensing techniques and secondary design issues for sub-90nm caches. ESSCIRC 2003: 413-416 - 2002
- [j7]Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. IEEE J. Solid State Circuits 37(5): 624-632 (2002) - [j6]Atila Alvandpour, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A sub-130-nm conditional keeper technique. IEEE J. Solid State Circuits 37(5): 633-638 (2002) - [c18]Atila Alvandpour, Ram Krishnamurthy, Shekhar Borkar, A. Rahman, Clair Webb:
A burn-in tolerant dynamic circuit technique. CICC 2002: 81-84 - [c17]Ram K. Krishnamurthy, Atila Alvandpour, Vivek De, Shekhar Borkar:
High-performance and low-power challenges for sub-70 nm microprocessor circuits. CICC 2002: 125-128 - 2001
- [c9]Atila Alvandpour, Ram Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Borkar:
A low-leakage dynamic multi-ported register file in 0.13mm CMOS. ISLPED 2001: 68-71
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