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Youn-Long Lin
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Publications
- 1993
- [j12]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(3): 410-424 (1993) - [j11]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
PLS: a scheduler for pipeline synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1279-1286 (1993) - 1991
- [j8]Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao:
Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40(6): 706-713 (1991) - [j7]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: a CMOS cell compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 994-1005 (1991) - [c10]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC 1991: 481-486 - [c9]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
Scheduling for Functional Pipelining and Loop Winding. DAC 1991: 764-769 - 1990
- [j5]Youn-Long Lin, Yu-Chin Hsu:
A new algorithm for tile generation. Integr. 9(3): 259-269 (1990) - [j4]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
Hybrid routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 151-157 (1990) - [j3]Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu:
A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 781-786 (1990) - [c8]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC 1990: 65-70 - [c7]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: A Cell Layout Generator. DAC 1990: 474-479 - [c6]Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu:
Data Path Allocation Based on Bipartite Weighted Matching. DAC 1990: 499-504 - 1989
- [j2]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
SILK: a simulated evolution router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10): 1108-1114 (1989) - [c5]Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin:
A new integer linear programming formulation for the scheduling problem in data path synthesis. ICCAD 1989: 20-23 - [c4]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An optimal transistor-chaining algorithm for CMOS cell layout. ICCAD 1989: 344-347 - [c3]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
Routing using a pyramid data structure. ICCAD 1989: 436-439 - 1988
- [c2]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
A detailed router based on simulated evolution. ICCAD 1988: 38-41
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