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Xijiang Lin
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Publications
- 2016
- [c41]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Transistor stuck-on fault detection tests for digital CMOS circuits. ETS 2016: 1-6 - 2015
- [c40]Xijiang Lin, Wu-Tung Cheng, Janusz Rajski:
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS 2015: 97-102 - [c38]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSID 2015: 399-404 - 2014
- [c37]Xijiang Lin, Mark Kassab, Janusz Rajski:
Using dynamic shift to reduce test data volume in high-compression designs. ETS 2014: 1-6 - 2012
- [c35]Xijiang Lin, Janusz Rajski:
On Utilizing Test Cube Properties to Reduce Test Data Volume Further. Asian Test Symposium 2012: 83-88 - 2011
- [c33]Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer:
Power Aware Embedded Test. Asian Test Symposium 2011: 511-516 - 2010
- [c31]Xijiang Lin, Janusz Rajski:
Adaptive Low Shift Power Test Pattern Generator for Logic BIST. Asian Test Symposium 2010: 355-360 - [c29]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab:
Low capture power at-speed test in EDT environment. ITC 2010: 714-723 - 2009
- [j4]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1742-1755 (2009) - 2008
- [c26]Xijiang Lin, Janusz Rajski:
Test Power Reduction by Blocking Scan Cell Outputs. ATS 2008: 329-336 - [c25]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10 - [c24]Xijiang Lin, Janusz Rajski:
Test Generation for Interconnect Opens. ITC 2008: 1-7 - 2007
- [j2]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. 24(3): 268-275 (2007) - [c21]Xijiang Lin, Mark Kassab, Janusz Rajski:
Test Generation for Timing-Critical Transition Faults. ATS 2007: 493-500 - [c20]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798 - 2006
- [c19]Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo:
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS 2006: 139-146 - [c18]Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC 2006: 1-10 - [c17]Xijiang Lin, Janusz Rajski:
The Impacts of Untestable Defects on Transition Fault Testing. VTS 2006: 2-7 - [c16]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348 - 2005
- [c15]Xijiang Lin, Janusz Rajski:
Propagation delay fault: a new fault model to test delay faults. ASP-DAC 2005: 178-183 - 2003
- [j1]Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli:
High-Frequency, At-Speed Scan Testing. IEEE Des. Test Comput. 20(5): 17-25 (2003) - 2002
- [c11]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93 - 2001
- [c8]Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097
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