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Jae-Joon Kim
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Publications
- 2024
- [i10]Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. CoRR abs/2402.09025 (2024) - 2023
- [c52]Changhun Lee, Hyungjun Kim, Eunhyeok Park, Jae-Joon Kim:
INSTA-BNN: Binary Neural Network with INSTAnce-aware Threshold. ICCV 2023: 17279-17288 - [c50]Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Taesu Kim, Daehyun Ahn, Hyungjun Kim, Jae-Joon Kim:
Leveraging Early-Stage Robustness in Diffusion Models for Efficient and High-Quality Image Synthesis. NeurIPS 2023 - [c49]Daehyun Ahn, Hyungjun Kim, Taesu Kim, Eunhyeok Park, Jae-Joon Kim:
Searching for Robust Binary Neural Networks via Bimodal Parameter Perturbation. WACV 2023: 2409-2418 - [i9]Jiwoong Choi, Minkyu Kim, Daehyun Ahn, Taesu Kim, Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Jae-Joon Kim, Hyungjun Kim:
Squeezing Large-Scale Diffusion Models for Mobile. CoRR abs/2307.01193 (2023) - 2022
- [j25]Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim:
Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators. ACM J. Emerg. Technol. Comput. Syst. 18(4): 75:1-75:19 (2022) - [j24]Sungju Ryu, Hyungjun Kim, Wooseok Yi, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim:
BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks. IEEE J. Solid State Circuits 57(6): 1924-1935 (2022) - [c48]Nameun Kang, Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim:
TAIM: ternary activation in-memory computing hardware with 6T SRAM array. DAC 2022: 1081-1086 - [i8]Changhun Lee, Hyungjun Kim, Eunhyeok Park, Jae-Joon Kim:
INSTA-BNN: Binary Neural Network with INSTAnce-aware Threshold. CoRR abs/2204.07439 (2022) - 2021
- [j22]Daehyun Ahn, Hyunmyung Oh, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators. IEEE Access 9: 141961-141969 (2021) - [c46]Hyunmyung Oh, Hyungjun Kim, Nameun Kang, Yulhwa Kim, Jihoon Park, Jae-Joon Kim:
Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks. AICAS 2021: 1-4 - [c45]Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim:
Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS. A-SSCC 2021: 1-3 - [c44]Hyungjun Kim, Jihoon Park, Changhun Lee, Jae-Joon Kim:
Improving Accuracy of Binary Neural Networks Using Unbalanced Activation Distribution. CVPR 2021: 7862-7871 - [c42]Yulhwa Kim, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim:
Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. DATE 2021: 856-861 - 2020
- [c40]Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim:
A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS. CICC 2020: 1-4 - [c38]Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim:
Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead. DAC 2020: 1-6 - [c36]Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim:
Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization. ICCAD 2020: 94:1-94:9 - [c35]Hyungjun Kim, Kyungsu Kim, Jinseok Kim, Jae-Joon Kim:
BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations. ICLR 2020 - [i7]Hyungjun Kim, Kyungsu Kim, Jinseok Kim, Jae-Joon Kim:
BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations. CoRR abs/2002.06517 (2020) - [i5]Hyungjun Kim, Jihoon Park, Changhun Lee, Jae-Joon Kim:
Improving Accuracy of Binary Neural Networks using Unbalanced Activation Distribution. CoRR abs/2012.00938 (2020) - 2019
- [c31]Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
In-memory batch-normalization for resistive memory based binary neural network hardware. ASP-DAC 2019: 645-650 - [c28]Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jae-Joon Kim:
BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation. DAC 2019: 84 - [c24]Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim:
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array. VLSI Circuits 2019: 118- - [i4]Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim:
BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function. CoRR abs/1903.09807 (2019) - [i3]Hyungjun Kim, Malte J. Rasch, Tayfun Gokmen, Takashi Ando, Hiroyuki Miyazoe, Jae-Joon Kim, John Rozen, Seyoung Kim:
Zero-shifting Technique for Deep Neural Network Training on Resistive Cross-point Arrays. CoRR abs/1907.10228 (2019) - 2018
- [j14]Hyungjun Kim, Taesu Kim, Jinseok Kim, Jae-Joon Kim:
Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics. ACM J. Emerg. Technol. Comput. Syst. 14(2): 15:1-15:17 (2018) - [c20]Yulhwa Kim, Hyungjun Kim, Daehyun Ahn, Jae-Joon Kim:
Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array. ISLPED 2018: 41:1-41:6 - [i2]Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim:
Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators. CoRR abs/1811.02187 (2018) - 2017
- [i1]Hyungjun Kim, Taesu Kim, Jinseok Kim, Jae-Joon Kim:
Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics. CoRR abs/1703.10642 (2017)
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last updated on 2024-04-25 02:41 CEST by the dblp team
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