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Yaw-Shih Shieh

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Hsi-Chin Hsin

> Home > Persons > Yaw-Shih Shieh

Publications

2012
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  - journals/cmmm/JuangHSSC12
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  - https://dblp.org/rec/journals/cmmm/JuangHSSC12
Ying-Shen Juang, Hsi-Chin Hsin, Tze-Yun Sung, Yaw-Shih Shieh, Carlo Cattani:
A Rate-Distortion-Based Merging Algorithm for Compressed Image Segmentation. Comput. Math. Methods Medicine 2012: 648320:1-648320:7 (2012)
[j2]
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  - journals/cmmm/KoCSHS12
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Lu-Ting Ko, Jwu-E Chen, Yaw-Shih Shieh, Hsi-Chin Hsin, Tze-Yun Sung:
Nested Quantization Index Modulation for Reversible Watermarking and Its Application to Healthcare Information Management Systems. Comput. Math. Methods Medicine 2012: 839161:1-839161:8 (2012)
[j1]
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  - journals/cmmm/HsinSS12
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Hsi-Chin Hsin, Tze-Yun Sung, Yaw-Shih Shieh:
An Adaptive Coding Pass Scanning Algorithm for Optimal Rate Control in Biomedical Images. Comput. Math. Methods Medicine 2012: 935914:1-935914:7 (2012)
[c5]
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  dblp key:
  - conf/icassp/HsinSS12
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Hsi-Chin Hsin, Tze-Yun Sung, Yaw-Shih Shieh:
A fast MQ table based merging algorithm for image segmentation. ICASSP 2012: 1009-1012
2006
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  - conf/pdcat/SungSYH06
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  - https://dblp.org/rec/conf/pdcat/SungSYH06
Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin:
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering. PDCAT 2006: 44-49
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  - conf/pdcat/SungSYH06a
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Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin:
Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters. PDCAT 2006: 185-190
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  - conf/pdcat/SungSYH06b
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Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin:
High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation. PDCAT 2006: 191-196
[c1]
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  - conf/psivt/SungSSH06
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Tze-Yun Sung, Mao-Jen Sun, Yaw-Shih Shieh, Hsi-Chin Hsin:
Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation. PSIVT 2006: 802-811

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